/*
  * dts file for Xilinx ZynqMP
  *
- * (C) Copyright 2014 - 2019, Xilinx, Inc.
+ * (C) Copyright 2014 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  *
                        power-domains = <&zynqmp_firmware PD_UART_1>;
                };
 
-               usb0: usb@fe200000 {
-                       compatible = "snps,dwc3";
+               usb0: usb@ff9d0000 {
+                       #address-cells = <2>;
+                       #size-cells = <2>;
                        status = "disabled";
-                       interrupt-parent = <&gic>;
-                       interrupts = <0 65 4>;
-                       reg = <0x0 0xfe200000 0x0 0x40000>;
-                       clock-names = "clk_xin", "clk_ahb";
+                       compatible = "xlnx,zynqmp-dwc3";
+                       reg = <0x0 0xff9d0000 0x0 0x100>;
+                       clock-names = "bus_clk", "ref_clk";
                        power-domains = <&zynqmp_firmware PD_USB_0>;
+                       resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
+                                <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
+                                <&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
+                       reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
+                       ranges;
+
+                       dwc3_0: usb@fe200000 {
+                               compatible = "snps,dwc3";
+                               reg = <0x0 0xfe200000 0x0 0x40000>;
+                               interrupt-parent = <&gic>;
+                               interrupt-names = "dwc_usb3", "otg";
+                               interrupts = <0 65 4>, <0 69 4>;
+                               #stream-id-cells = <1>;
+                               iommus = <&smmu 0x860>;
+                               snps,quirk-frame-length-adjustment = <0x20>;
+                               /* dma-coherent; */
+                       };
                };
 
-               usb1: usb@fe300000 {
-                       compatible = "snps,dwc3";
+               usb1: usb@ff9e0000 {
+                       #address-cells = <2>;
+                       #size-cells = <2>;
                        status = "disabled";
-                       interrupt-parent = <&gic>;
-                       interrupts = <0 70 4>;
-                       reg = <0x0 0xfe300000 0x0 0x40000>;
-                       clock-names = "clk_xin", "clk_ahb";
+                       compatible = "xlnx,zynqmp-dwc3";
+                       reg = <0x0 0xff9e0000 0x0 0x100>;
+                       clock-names = "bus_clk", "ref_clk";
                        power-domains = <&zynqmp_firmware PD_USB_1>;
+                       resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
+                                <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
+                                <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
+                       reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
+                       ranges;
+
+                       dwc3_1: usb@fe300000 {
+                               compatible = "snps,dwc3";
+                               reg = <0x0 0xfe300000 0x0 0x40000>;
+                               interrupt-parent = <&gic>;
+                               interrupt-names = "dwc_usb3", "otg";
+                               interrupts = <0 70 4>, <0 74 4>;
+                               #stream-id-cells = <1>;
+                               iommus = <&smmu 0x861>;
+                               snps,quirk-frame-length-adjustment = <0x20>;
+                               /* dma-coherent; */
+                       };
                };
 
                watchdog0: watchdog@fd4d0000 {