drm/xe: flush engine buffers before signalling user fence on all engines

Tests show that user fence signalling requires kind of write barrier,
otherwise not all writes performed by the workload will be available
to userspace. It is already done for render and compute, we need it
also for the rest: video, gsc, copy.

Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240605-fix_user_fence_posted-v3-2-06e7932f784a@intel.com
(cherry picked from commit 3ad7d18c5dad75ed38098c7cc3bc9594b4701399)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index d42b3f33bd7a2bfb7cf779cf462b5d133c2e43b3..aca7a9af6e846e329c9057a7369b9eff2d9b4d11 100644 (file)
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -80,6 +80,16 @@ static int emit_store_imm_ggtt(u32 addr, u32 value, u32 *dw, int i)
        return i;
 }
 
+static int emit_flush_dw(u32 *dw, int i)
+{
+       dw[i++] = MI_FLUSH_DW | MI_FLUSH_IMM_DW;
+       dw[i++] = 0;
+       dw[i++] = 0;
+       dw[i++] = 0;
+
+       return i;
+}
+
 static int emit_flush_imm_ggtt(u32 addr, u32 value, bool invalidate_tlb,
                               u32 *dw, int i)
 {
@@ -234,10 +244,12 @@ static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc
 
        i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
 
-       if (job->user_fence.used)
+       if (job->user_fence.used) {
+               i = emit_flush_dw(dw, i);
                i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
                                                job->user_fence.value,
                                                dw, i);
+       }
 
        i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i);
 
@@ -293,10 +305,12 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
 
        i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
 
-       if (job->user_fence.used)
+       if (job->user_fence.used) {
+               i = emit_flush_dw(dw, i);
                i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
                                                job->user_fence.value,
                                                dw, i);
+       }
 
        i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i);