drm/amd/display: add missing ABM register offsets

[Why]
Some ABM registers don't exist on DCN 3.01, so are
missing from its register offset list. However,
this list was copied to later versions of DCN that
do have these registers. As a result, they're
inaccessible from the driver on those DCN versions
even though they exist.

[How]
Add the missing ABM register offsets to DCN 3.02+

Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index 456fadbbfac7077ad6cce072e2e67c4899356bd5..b699d1b2ba83c7ab15846477f84a6708680463c3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -96,6 +96,22 @@
        SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
        NBIO_SR(BIOS_SCRATCH_2)
 
+#define ABM_DCN302_REG_LIST(id)\
+       ABM_COMMON_REG_LIST_DCE_BASE(), \
+       SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
+       SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
+       SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
+       SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
+       SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
+       SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
+       SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
+       SRI(BL1_PWM_USER_LEVEL, ABM, id), \
+       SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
+       SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
+       SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
+       SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
+       NBIO_SR(BIOS_SCRATCH_2)
+
 #define ABM_DCN30_REG_LIST(id)\
        ABM_COMMON_REG_LIST_DCE_BASE(), \
        SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \

diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index 7d3ff5d4440235e2f32e219eac69eea17c09e27c..5cd55e8573f701b900fa9031f8f76382539271c5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -1462,7 +1462,7 @@ static const struct dccg_mask dccg_mask = {
 };
 
 #define abm_regs(id)\
-               [id] = { ABM_DCN301_REG_LIST(id) }
+               [id] = { ABM_DCN302_REG_LIST(id) }
 
 static const struct dce_abm_registers abm_regs[] = {
                abm_regs(0),

diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
index dd38796ba30ad0ceb32636aa5b55e5703e39b321..2ce6eae7535d4fa4b2b6b2dc57753c80ad7acd3f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
@@ -1394,7 +1394,7 @@ static const struct dccg_mask dccg_mask = {
 };
 
 #define abm_regs(id)\
-               [id] = { ABM_DCN301_REG_LIST(id) }
+               [id] = { ABM_DCN302_REG_LIST(id) }
 
 static const struct dce_abm_registers abm_regs[] = {
                abm_regs(0),

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 463e96f8f14c7668c42b384cf7a095e35ac45210..5a4d33836f5e0431cd6658e9b0cdb374ef5b8993 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -366,7 +366,7 @@ static const struct dce110_clk_src_mask cs_mask = {
 
 #define abm_regs(id)\
 [id] = {\
-               ABM_DCN301_REG_LIST(id)\
+               ABM_DCN302_REG_LIST(id)\
 }
 
 static const struct dce_abm_registers abm_regs[] = {