drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field

ICL+ adds changes the PLANE_CTL_FORMAT field from [27:24] to [27:23],
however, all existing PLANE_CTL_FORMAT_* definitions still map to the
correct values.  Add an ICL_PLANE_CTL_FORMAT_MASK definition, and use
that for masking for the conversion to fourcc.

v2: No changes

v3: Change new definition name, drop comment (Rodrigo)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180130134918.32283-8-paulo.r.zanoni@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 54468b9c4dc53a7d0f9b341433413ce5dcbc9a24..82815b69dfbf14bae9b19bbd3318a02a7a54a805 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6349,6 +6349,11 @@ enum {
 #define _PLANE_CTL_3_A                         0x70380
 #define   PLANE_CTL_ENABLE                     (1 << 31)
 #define   PLANE_CTL_PIPE_GAMMA_ENABLE          (1 << 30)   /* Pre-GLK */
+/*
+ * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
+ * expanded to include bit 23 as well. However, the shift-24 based values
+ * correctly map to the same formats in ICL, as long as bit 23 is set to 0
+ */
 #define   PLANE_CTL_FORMAT_MASK                        (0xf << 24)
 #define   PLANE_CTL_FORMAT_YUV422              (  0 << 24)
 #define   PLANE_CTL_FORMAT_NV12                        (  1 << 24)
@@ -6358,6 +6363,7 @@ enum {
 #define   PLANE_CTL_FORMAT_AYUV                        (  8 << 24)
 #define   PLANE_CTL_FORMAT_INDEXED             ( 12 << 24)
 #define   PLANE_CTL_FORMAT_RGB_565             ( 14 << 24)
+#define   ICL_PLANE_CTL_FORMAT_MASK            (0x1f << 23)
 #define   PLANE_CTL_PIPE_CSC_ENABLE            (1 << 23) /* Pre-GLK */
 #define   PLANE_CTL_KEY_ENABLE_MASK            (0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE          (  1 << 21)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 217badde15fa33b296c5b20917b0da5541a28032..e79b9242eb66c5b1a8982141a3986646cfb90bff 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8527,7 +8527,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
        val = I915_READ(PLANE_CTL(pipe, plane_id));
 
-       pixel_format = val & PLANE_CTL_FORMAT_MASK;
+       if (INTEL_GEN(dev_priv) >= 11)
+               pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
+       else
+               pixel_format = val & PLANE_CTL_FORMAT_MASK;
 
        if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
                alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));