drm/amdkfd: Use better name for sdma queue non HWS path

The old name is prone to confusion. The register offset is for a RLC queue
rather than a SDMA engine. The value is not a base address, but a
register offset.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
index 0fcf7b42c50868bbd6e55f7a529095c5351215ca..68acb8d5296ebe999f5a3af16d99c65ee085815f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
@@ -69,11 +69,11 @@ static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
        return (struct v9_sdma_mqd *)mqd;
 }
 
-static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
+static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
                                unsigned int engine_id,
                                unsigned int queue_id)
 {
-       uint32_t base[8] = {
+       uint32_t sdma_engine_reg_base[8] = {
                SOC15_REG_OFFSET(SDMA0, 0,
                                 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
                SOC15_REG_OFFSET(SDMA1, 0,
@@ -91,12 +91,12 @@ static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
                SOC15_REG_OFFSET(SDMA7, 0,
                                 mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL
        };
-       uint32_t retval;
 
-       retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
-                                              mmSDMA0_RLC0_RB_CNTL);
+       uint32_t retval = sdma_engine_reg_base[engine_id]
+               + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
 
-       pr_debug("sdma base address: 0x%x\n", retval);
+       pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
+                       queue_id, retval);
 
        return retval;
 }
@@ -106,22 +106,22 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct v9_sdma_mqd *m;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        unsigned long end_jiffies;
        uint32_t data;
        uint64_t data64;
        uint64_t __user *wptr64 = (uint64_t __user *)wptr;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
                                            m->sdma_queue_id);
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
                m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 
        end_jiffies = msecs_to_jiffies(2000) + jiffies;
        while (true) {
-               data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+               data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
                if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
                        break;
                if (time_after(jiffies, end_jiffies)) {
@@ -131,41 +131,42 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
                usleep_range(500, 1000);
        }
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
               m->sdmax_rlcx_doorbell_offset);
 
        data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
                             ENABLE, 1);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
+                               m->sdmax_rlcx_rb_rptr);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
                                m->sdmax_rlcx_rb_rptr_hi);
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
        if (read_user_wptr(mm, wptr64, data64)) {
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
                       lower_32_bits(data64));
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
                       upper_32_bits(data64));
        } else {
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
                       m->sdmax_rlcx_rb_rptr);
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
                       m->sdmax_rlcx_rb_rptr_hi);
        }
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
                        m->sdmax_rlcx_rb_base_hi);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
                        m->sdmax_rlcx_rb_rptr_addr_lo);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
                        m->sdmax_rlcx_rb_rptr_addr_hi);
 
        data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
                             RB_ENABLE, 1);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
 
        return 0;
 }
@@ -175,7 +176,8 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
                             uint32_t (**dump)[2], uint32_t *n_regs)
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
-       uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id);
+       uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
+                       engine_id, queue_id);
        uint32_t i = 0, reg;
 #undef HQD_N_REGS
 #define HQD_N_REGS (19+6+7+10)
@@ -185,15 +187,15 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
                return -ENOMEM;
 
        for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
-               DUMP_REG(sdma_base_addr + reg);
+               DUMP_REG(sdma_rlc_reg_offset + reg);
        for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
-               DUMP_REG(sdma_base_addr + reg);
+               DUMP_REG(sdma_rlc_reg_offset + reg);
        for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
             reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
-               DUMP_REG(sdma_base_addr + reg);
+               DUMP_REG(sdma_rlc_reg_offset + reg);
        for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
             reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
-               DUMP_REG(sdma_base_addr + reg);
+               DUMP_REG(sdma_rlc_reg_offset + reg);
 
        WARN_ON_ONCE(i != HQD_N_REGS);
        *n_regs = i;
@@ -205,14 +207,14 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct v9_sdma_mqd *m;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        uint32_t sdma_rlc_rb_cntl;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
                                            m->sdma_queue_id);
 
-       sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
+       sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
 
        if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
                return true;
@@ -225,20 +227,20 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct v9_sdma_mqd *m;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        uint32_t temp;
        unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
                                            m->sdma_queue_id);
 
-       temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
+       temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
        temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
 
        while (true) {
-               temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+               temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
                if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
                        break;
                if (time_after(jiffies, end_jiffies)) {
@@ -248,14 +250,14 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
                usleep_range(500, 1000);
        }
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
-               RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
+               RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
                SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 
-       m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
+       m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
        m->sdmax_rlcx_rb_rptr_hi =
-               RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI);
+               RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 7c21f067c8dfe53c7e2e059b3b346e540d3b0e9a..fe5b702c75ce9f018061ef3c170889aacaf92317 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -307,11 +307,11 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
        return 0;
 }
 
-static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
+static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
                                unsigned int engine_id,
                                unsigned int queue_id)
 {
-       uint32_t base[2] = {
+       uint32_t sdma_engine_reg_base[2] = {
                SOC15_REG_OFFSET(SDMA0, 0,
                                 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
                /* On gfx10, mmSDMA1_xxx registers are defined NOT based
@@ -323,12 +323,12 @@ static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
                SOC15_REG_OFFSET(SDMA1, 0,
                                 mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL
        };
-       uint32_t retval;
 
-       retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
-                                              mmSDMA0_RLC0_RB_CNTL);
+       uint32_t retval = sdma_engine_reg_base[engine_id]
+               + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
 
-       pr_debug("sdma base address: 0x%x\n", retval);
+       pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
+                       queue_id, retval);
 
        return retval;
 }
@@ -489,23 +489,22 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct v10_sdma_mqd *m;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        unsigned long end_jiffies;
        uint32_t data;
        uint64_t data64;
        uint64_t __user *wptr64 = (uint64_t __user *)wptr;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
                                            m->sdma_queue_id);
-       pr_debug("sdma load base addr %x for engine %d, queue %d\n", sdma_base_addr, m->sdma_engine_id, m->sdma_queue_id);
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
                m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 
        end_jiffies = msecs_to_jiffies(2000) + jiffies;
        while (true) {
-               data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+               data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
                if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
                        break;
                if (time_after(jiffies, end_jiffies)) {
@@ -515,41 +514,42 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
                usleep_range(500, 1000);
        }
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
               m->sdmax_rlcx_doorbell_offset);
 
        data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
                             ENABLE, 1);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
+                               m->sdmax_rlcx_rb_rptr);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
                                m->sdmax_rlcx_rb_rptr_hi);
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
        if (read_user_wptr(mm, wptr64, data64)) {
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
                       lower_32_bits(data64));
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
                       upper_32_bits(data64));
        } else {
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
                       m->sdmax_rlcx_rb_rptr);
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
                       m->sdmax_rlcx_rb_rptr_hi);
        }
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
                        m->sdmax_rlcx_rb_base_hi);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
                        m->sdmax_rlcx_rb_rptr_addr_lo);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
                        m->sdmax_rlcx_rb_rptr_addr_hi);
 
        data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
                             RB_ENABLE, 1);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
 
        return 0;
 }
@@ -559,28 +559,26 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
                             uint32_t (**dump)[2], uint32_t *n_regs)
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
-       uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id);
+       uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
+                       engine_id, queue_id);
        uint32_t i = 0, reg;
 #undef HQD_N_REGS
 #define HQD_N_REGS (19+6+7+10)
 
-       pr_debug("sdma dump engine id %d queue_id %d\n", engine_id, queue_id);
-       pr_debug("sdma base addr %x\n", sdma_base_addr);
-
        *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
        if (*dump == NULL)
                return -ENOMEM;
 
        for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
-               DUMP_REG(sdma_base_addr + reg);
+               DUMP_REG(sdma_rlc_reg_offset + reg);
        for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
-               DUMP_REG(sdma_base_addr + reg);
+               DUMP_REG(sdma_rlc_reg_offset + reg);
        for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
             reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
-               DUMP_REG(sdma_base_addr + reg);
+               DUMP_REG(sdma_rlc_reg_offset + reg);
        for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
             reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
-               DUMP_REG(sdma_base_addr + reg);
+               DUMP_REG(sdma_rlc_reg_offset + reg);
 
        WARN_ON_ONCE(i != HQD_N_REGS);
        *n_regs = i;
@@ -614,14 +612,14 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct v10_sdma_mqd *m;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        uint32_t sdma_rlc_rb_cntl;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
                                            m->sdma_queue_id);
 
-       sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
+       sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
 
        if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
                return true;
@@ -742,20 +740,20 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct v10_sdma_mqd *m;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        uint32_t temp;
        unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
                                            m->sdma_queue_id);
 
-       temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
+       temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
        temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
 
        while (true) {
-               temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+               temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
                if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
                        break;
                if (time_after(jiffies, end_jiffies)) {
@@ -765,14 +763,14 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
                usleep_range(500, 1000);
        }
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
-               RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
+               RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
                SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 
-       m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
+       m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
        m->sdmax_rlcx_rb_rptr_hi =
-               RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI);
+               RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 4c4e6b7e74072427a3b4c1627c683a61feff04da..8c97be0ff396a9353b531347ed88e7f59ab1a2f0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -303,14 +303,15 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
        return 0;
 }
 
-static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
+static inline uint32_t get_sdma_rlc_reg_offset(struct cik_sdma_rlc_registers *m)
 {
        uint32_t retval;
 
        retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
                        m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
 
-       pr_debug("sdma base address: 0x%x\n", retval);
+       pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n",
+                       m->sdma_engine_id, m->sdma_queue_id, retval);
 
        return retval;
 }
@@ -413,18 +414,18 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct cik_sdma_rlc_registers *m;
        unsigned long end_jiffies;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        uint32_t data;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(m);
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
                m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 
        end_jiffies = msecs_to_jiffies(2000) + jiffies;
        while (true) {
-               data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+               data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
                if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
                        break;
                if (time_after(jiffies, end_jiffies)) {
@@ -436,28 +437,29 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 
        data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
                             ENABLE, 1);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdma_rlc_rb_rptr);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
+                               m->sdma_rlc_rb_rptr);
 
        if (read_user_wptr(mm, wptr, data))
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
        else
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
                       m->sdma_rlc_rb_rptr);
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
                                m->sdma_rlc_virtual_addr);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
                        m->sdma_rlc_rb_base_hi);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
                        m->sdma_rlc_rb_rptr_addr_lo);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
                        m->sdma_rlc_rb_rptr_addr_hi);
 
        data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
                             RB_ENABLE, 1);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
 
        return 0;
 }
@@ -515,13 +517,13 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct cik_sdma_rlc_registers *m;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        uint32_t sdma_rlc_rb_cntl;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(m);
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
 
-       sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
+       sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
 
        if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
                return true;
@@ -636,19 +638,19 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct cik_sdma_rlc_registers *m;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        uint32_t temp;
        unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(m);
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
 
-       temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
+       temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
        temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
 
        while (true) {
-               temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+               temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
                if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
                        break;
                if (time_after(jiffies, end_jiffies)) {
@@ -658,12 +660,12 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
                usleep_range(500, 1000);
        }
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
-               RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
+               RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
                SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 
-       m->sdma_rlc_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
+       m->sdma_rlc_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index 4894108c5d588f4e14de8192064fc5655b22c39c..240441e15d521a1abc3f076108e07442a3784d6a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -260,13 +260,15 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
        return 0;
 }
 
-static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m)
+static inline uint32_t get_sdma_rlc_reg_offset(struct vi_sdma_mqd *m)
 {
        uint32_t retval;
 
        retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
                m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
-       pr_debug("sdma base address: 0x%x\n", retval);
+
+       pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n",
+                       m->sdma_engine_id, m->sdma_queue_id, retval);
 
        return retval;
 }
@@ -398,17 +400,17 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct vi_sdma_mqd *m;
        unsigned long end_jiffies;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        uint32_t data;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(m);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
                m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 
        end_jiffies = msecs_to_jiffies(2000) + jiffies;
        while (true) {
-               data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+               data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
                if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
                        break;
                if (time_after(jiffies, end_jiffies)) {
@@ -420,28 +422,29 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 
        data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
                             ENABLE, 1);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
+                               m->sdmax_rlcx_rb_rptr);
 
        if (read_user_wptr(mm, wptr, data))
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
        else
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
                       m->sdmax_rlcx_rb_rptr);
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
                                m->sdmax_rlcx_virtual_addr);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
                        m->sdmax_rlcx_rb_base_hi);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
                        m->sdmax_rlcx_rb_rptr_addr_lo);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
                        m->sdmax_rlcx_rb_rptr_addr_hi);
 
        data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
                             RB_ENABLE, 1);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
 
        return 0;
 }
@@ -508,13 +511,13 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct vi_sdma_mqd *m;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        uint32_t sdma_rlc_rb_cntl;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(m);
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
 
-       sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
+       sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
 
        if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
                return true;
@@ -632,19 +635,19 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct vi_sdma_mqd *m;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        uint32_t temp;
        unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(m);
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
 
-       temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
+       temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
        temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
 
        while (true) {
-               temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+               temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
                if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
                        break;
                if (time_after(jiffies, end_jiffies)) {
@@ -654,12 +657,12 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
                usleep_range(500, 1000);
        }
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
-               RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
+               RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
                SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 
-       m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
+       m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index acd7296c7e52e62964f4a00aa5f5f5aecb7f876d..b83b83bb28a9575ab2b462b50bc0b94bbbebf574 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -226,22 +226,21 @@ int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
        return 0;
 }
 
-static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
+static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
                                unsigned int engine_id,
                                unsigned int queue_id)
 {
-       uint32_t base[2] = {
+       uint32_t sdma_engine_reg_base[2] = {
                SOC15_REG_OFFSET(SDMA0, 0,
                                 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
                SOC15_REG_OFFSET(SDMA1, 0,
                                 mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL
        };
-       uint32_t retval;
+       uint32_t retval = sdma_engine_reg_base[engine_id]
+               + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
 
-       retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
-                                              mmSDMA0_RLC0_RB_CNTL);
-
-       pr_debug("sdma base address: 0x%x\n", retval);
+       pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
+                       queue_id, retval);
 
        return retval;
 }
@@ -388,22 +387,22 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct v9_sdma_mqd *m;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        unsigned long end_jiffies;
        uint32_t data;
        uint64_t data64;
        uint64_t __user *wptr64 = (uint64_t __user *)wptr;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
                                            m->sdma_queue_id);
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
                m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 
        end_jiffies = msecs_to_jiffies(2000) + jiffies;
        while (true) {
-               data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+               data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
                if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
                        break;
                if (time_after(jiffies, end_jiffies)) {
@@ -413,41 +412,42 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
                usleep_range(500, 1000);
        }
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
               m->sdmax_rlcx_doorbell_offset);
 
        data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
                             ENABLE, 1);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
+                               m->sdmax_rlcx_rb_rptr);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
                                m->sdmax_rlcx_rb_rptr_hi);
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
        if (read_user_wptr(mm, wptr64, data64)) {
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
                       lower_32_bits(data64));
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
                       upper_32_bits(data64));
        } else {
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
                       m->sdmax_rlcx_rb_rptr);
-               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
+               WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
                       m->sdmax_rlcx_rb_rptr_hi);
        }
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
                        m->sdmax_rlcx_rb_base_hi);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
                        m->sdmax_rlcx_rb_rptr_addr_lo);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
                        m->sdmax_rlcx_rb_rptr_addr_hi);
 
        data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
                             RB_ENABLE, 1);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
 
        return 0;
 }
@@ -457,7 +457,8 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
                             uint32_t (**dump)[2], uint32_t *n_regs)
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
-       uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id);
+       uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
+                       engine_id, queue_id);
        uint32_t i = 0, reg;
 #undef HQD_N_REGS
 #define HQD_N_REGS (19+6+7+10)
@@ -467,15 +468,15 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
                return -ENOMEM;
 
        for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
-               DUMP_REG(sdma_base_addr + reg);
+               DUMP_REG(sdma_rlc_reg_offset + reg);
        for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
-               DUMP_REG(sdma_base_addr + reg);
+               DUMP_REG(sdma_rlc_reg_offset + reg);
        for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
             reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
-               DUMP_REG(sdma_base_addr + reg);
+               DUMP_REG(sdma_rlc_reg_offset + reg);
        for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
             reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
-               DUMP_REG(sdma_base_addr + reg);
+               DUMP_REG(sdma_rlc_reg_offset + reg);
 
        WARN_ON_ONCE(i != HQD_N_REGS);
        *n_regs = i;
@@ -509,14 +510,14 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct v9_sdma_mqd *m;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        uint32_t sdma_rlc_rb_cntl;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
                                            m->sdma_queue_id);
 
-       sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
+       sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
 
        if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
                return true;
@@ -579,20 +580,20 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        struct v9_sdma_mqd *m;
-       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_reg_offset;
        uint32_t temp;
        unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 
        m = get_sdma_mqd(mqd);
-       sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+       sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
                                            m->sdma_queue_id);
 
-       temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
+       temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
        temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
 
        while (true) {
-               temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+               temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
                if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
                        break;
                if (time_after(jiffies, end_jiffies)) {
@@ -602,14 +603,14 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
                usleep_range(500, 1000);
        }
 
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
-       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
-               RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
+       WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
+               RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
                SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 
-       m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
+       m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
        m->sdmax_rlcx_rb_rptr_hi =
-               RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI);
+               RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
 
        return 0;
 }