for (gpio = 0; gpio < dev->gpio_chip.ngpio; gpio++) {
                int irq = gpio + dev->irq_base;
-               set_irq_chip_data(irq, dev);
-               set_irq_chip_and_handler(irq, &adp5588_irq_chip,
+               irq_set_chip_data(irq, dev);
+               irq_set_chip_and_handler(irq, &adp5588_irq_chip,
                                         handle_level_irq);
-               set_irq_nested_thread(irq, 1);
+               irq_set_nested_thread(irq, 1);
 #ifdef CONFIG_ARM
                /*
                 * ARM needs us to explicitly flag the IRQ as VALID,
                 */
                set_irq_flags(irq, IRQF_VALID);
 #else
-               set_irq_noprobe(irq);
+               irq_set_noprobe(irq);
 #endif
        }
 
 
                        if (!(chip->dir_input & (1 << lvl)))
                                continue;
 
-                       set_irq_chip_data(irq, chip);
-                       set_irq_chip_and_handler(irq, &max732x_irq_chip,
+                       irq_set_chip_data(irq, chip);
+                       irq_set_chip_and_handler(irq, &max732x_irq_chip,
                                                 handle_edge_irq);
-                       set_irq_nested_thread(irq, 1);
+                       irq_set_nested_thread(irq, 1);
 #ifdef CONFIG_ARM
                        set_irq_flags(irq, IRQF_VALID);
 #else
-                       set_irq_noprobe(irq);
+                       irq_set_noprobe(irq);
 #endif
                }
 
 
                for (lvl = 0; lvl < chip->gpio_chip.ngpio; lvl++) {
                        int irq = lvl + chip->irq_base;
 
-                       set_irq_chip_data(irq, chip);
-                       set_irq_chip_and_handler(irq, &pca953x_irq_chip,
+                       irq_set_chip_data(irq, chip);
+                       irq_set_chip_and_handler(irq, &pca953x_irq_chip,
                                                 handle_edge_irq);
 #ifdef CONFIG_ARM
                        set_irq_flags(irq, IRQF_VALID);
 #else
-                       set_irq_noprobe(irq);
+                       irq_set_noprobe(irq);
 #endif
                }
 
 
 
 static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-       struct list_head *chip_list = get_irq_data(irq);
+       struct list_head *chip_list = irq_get_handler_data(irq);
        struct list_head *ptr;
        struct pl061_gpio *chip;
 
                ret = -ENODEV;
                goto iounmap;
        }
-       set_irq_chained_handler(irq, pl061_irq_handler);
+       irq_set_chained_handler(irq, pl061_irq_handler);
        if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */
                chip_list = kmalloc(sizeof(*chip_list), GFP_KERNEL);
                if (chip_list == NULL) {
                        goto iounmap;
                }
                INIT_LIST_HEAD(chip_list);
-               set_irq_data(irq, chip_list);
+               irq_set_handler_data(irq, chip_list);
        } else
-               chip_list = get_irq_data(irq);
+               chip_list = irq_get_handler_data(irq);
        list_add(&chip->list, chip_list);
 
        for (i = 0; i < PL061_GPIO_NR; i++) {
                else
                        pl061_direction_input(&chip->gc, i);
 
-               set_irq_chip(i+chip->irq_base, &pl061_irqchip);
-               set_irq_handler(i+chip->irq_base, handle_simple_irq);
+               irq_set_chip(i + chip->irq_base, &pl061_irqchip);
+               irq_set_handler(i + chip->irq_base, handle_simple_irq);
                set_irq_flags(i+chip->irq_base, IRQF_VALID);
-               set_irq_chip_data(i+chip->irq_base, chip);
+               irq_set_chip_data(i + chip->irq_base, chip);
        }
 
        return 0;
 
        int irq;
 
        for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
-               set_irq_chip_data(irq, stmpe_gpio);
-               set_irq_chip_and_handler(irq, &stmpe_gpio_irq_chip,
+               irq_set_chip_data(irq, stmpe_gpio);
+               irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
                                         handle_simple_irq);
-               set_irq_nested_thread(irq, 1);
+               irq_set_nested_thread(irq, 1);
 #ifdef CONFIG_ARM
                set_irq_flags(irq, IRQF_VALID);
 #else
-               set_irq_noprobe(irq);
+               irq_set_noprobe(irq);
 #endif
        }
 
 #ifdef CONFIG_ARM
                set_irq_flags(irq, 0);
 #endif
-               set_irq_chip_and_handler(irq, NULL, NULL);
-               set_irq_chip_data(irq, NULL);
+               irq_set_chip_and_handler(irq, NULL, NULL);
+               irq_set_chip_data(irq, NULL);
        }
 }
 
 
 
        for (n = 0; n < chip->dev_cfg->ngpios; ++n) {
                irq = irq_base + n;
-               set_irq_chip_and_handler(irq, &chip->irq_chip, handle_edge_irq);
-               set_irq_nested_thread(irq, 1);
+               irq_set_chip_and_handler(irq, &chip->irq_chip, handle_edge_irq);
+               irq_set_nested_thread(irq, 1);
 #ifdef CONFIG_ARM
                set_irq_flags(irq, IRQF_VALID);
 #else
-               set_irq_noprobe(irq);
+               irq_set_noprobe(irq);
 #endif
        }
 
 
        for (n = 0; n < chip->dev_cfg->ngpios; ++n) {
                irq = chip->irq_base + n;
-               set_irq_handler(irq, NULL);
-               set_irq_chip(irq, NULL);
+               irq_set_handler(irq, NULL);
+               irq_set_chip(irq, NULL);
        }
 }
 
 
        int irq;
 
        for (irq = base; irq < base + tc3589x_gpio->chip.ngpio; irq++) {
-               set_irq_chip_data(irq, tc3589x_gpio);
-               set_irq_chip_and_handler(irq, &tc3589x_gpio_irq_chip,
+               irq_set_chip_data(irq, tc3589x_gpio);
+               irq_set_chip_and_handler(irq, &tc3589x_gpio_irq_chip,
                                         handle_simple_irq);
-               set_irq_nested_thread(irq, 1);
+               irq_set_nested_thread(irq, 1);
 #ifdef CONFIG_ARM
                set_irq_flags(irq, IRQF_VALID);
 #else
-               set_irq_noprobe(irq);
+               irq_set_noprobe(irq);
 #endif
        }
 
 #ifdef CONFIG_ARM
                set_irq_flags(irq, 0);
 #endif
-               set_irq_chip_and_handler(irq, NULL, NULL);
-               set_irq_chip_data(irq, NULL);
+               irq_set_chip_and_handler(irq, NULL, NULL);
+               irq_set_chip_data(irq, NULL);
        }
 }
 
 
 
 static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
 {
-       struct timbgpio *tgpio = get_irq_data(irq);
+       struct timbgpio *tgpio = irq_get_handler_data(irq);
        unsigned long ipr;
        int offset;
 
                return 0;
 
        for (i = 0; i < pdata->nr_pins; i++) {
-               set_irq_chip_and_handler_name(tgpio->irq_base + i,
+               irq_set_chip_and_handler_name(tgpio->irq_base + i,
                        &timbgpio_irqchip, handle_simple_irq, "mux");
-               set_irq_chip_data(tgpio->irq_base + i, tgpio);
+               irq_set_chip_data(tgpio->irq_base + i, tgpio);
 #ifdef CONFIG_ARM
                set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE);
 #endif
        }
 
-       set_irq_data(irq, tgpio);
-       set_irq_chained_handler(irq, timbgpio_irq);
+       irq_set_handler_data(irq, tgpio);
+       irq_set_chained_handler(irq, timbgpio_irq);
 
        return 0;
 
        if (irq >= 0 && tgpio->irq_base > 0) {
                int i;
                for (i = 0; i < pdata->nr_pins; i++) {
-                       set_irq_chip(tgpio->irq_base + i, NULL);
-                       set_irq_chip_data(tgpio->irq_base + i, NULL);
+                       irq_set_chip(tgpio->irq_base + i, NULL);
+                       irq_set_chip_data(tgpio->irq_base + i, NULL);
                }
 
-               set_irq_handler(irq, NULL);
-               set_irq_data(irq, NULL);
+               irq_set_handler(irq, NULL);
+               irq_set_handler_data(irq, NULL);
        }
 
        err = gpiochip_remove(&tgpio->gpio);
 
                                        break;
                                }
                        }
-                       set_irq_chip_and_handler(GIU_IRQ(pin),
+                       irq_set_chip_and_handler(GIU_IRQ(pin),
                                                 &giuint_low_irq_chip,
                                                 handle_edge_irq);
                } else {
                        giu_clear(GIUINTTYPL, mask);
                        giu_clear(GIUINTHTSELL, mask);
-                       set_irq_chip_and_handler(GIU_IRQ(pin),
+                       irq_set_chip_and_handler(GIU_IRQ(pin),
                                                 &giuint_low_irq_chip,
                                                 handle_level_irq);
                }
                                        break;
                                }
                        }
-                       set_irq_chip_and_handler(GIU_IRQ(pin),
+                       irq_set_chip_and_handler(GIU_IRQ(pin),
                                                 &giuint_high_irq_chip,
                                                 handle_edge_irq);
                } else {
                        giu_clear(GIUINTTYPH, mask);
                        giu_clear(GIUINTHTSELH, mask);
-                       set_irq_chip_and_handler(GIU_IRQ(pin),
+                       irq_set_chip_and_handler(GIU_IRQ(pin),
                                                 &giuint_high_irq_chip,
                                                 handle_level_irq);
                }
                        chip = &giuint_high_irq_chip;
 
                if (trigger & (1 << pin))
-                       set_irq_chip_and_handler(i, chip, handle_edge_irq);
+                       irq_set_chip_and_handler(i, chip, handle_edge_irq);
                else
-                       set_irq_chip_and_handler(i, chip, handle_level_irq);
+                       irq_set_chip_and_handler(i, chip, handle_level_irq);
 
        }