drm/amd/display: Add pixel_clock to amd_pp_display_configuration

This commit adds the pixel_clock field to the display config
struct so that power management (DPM) can use it.

We currently don't have a proper bandwidth calculation on old
GPUs with DCE 6-10 because dce_calcs only supports DCE 11+.
So the power management (DPM) on these GPUs may need to make
ad-hoc decisions for display based on the pixel clock.

Also rename sym_clock to pixel_clock in dm_pp_single_disp_config
to avoid confusion with other code where the sym_clock refers to
the DisplayPort symbol clock.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index e5771f490f2e36d53b294a28cf06ddaf948cfa01..11b2ea6edf953114c6b3753fe2d089b94866b32f 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -98,6 +98,7 @@ bool dm_pp_apply_display_requirements(
                        const struct dm_pp_single_disp_config *dc_cfg =
                                                &pp_display_cfg->disp_configs[i];
                        adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1;
+                       adev->pm.pm_display_cfg.displays[i].pixel_clock = dc_cfg->pixel_clock;
                }
 
                amdgpu_dpm_display_configuration_change(adev, &adev->pm.pm_display_cfg);

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index 13cf415e38e5019462acbe97173b8d9e5225a15f..d50b9440210e46dc030846eb9787170418ca53f7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -164,7 +164,7 @@ void dce110_fill_display_configs(
                        stream->link->cur_link_settings.link_rate;
                cfg->link_settings.link_spread =
                        stream->link->cur_link_settings.link_spread;
-               cfg->sym_clock = stream->phy_pix_clk;
+               cfg->pixel_clock = stream->phy_pix_clk;
                /* Round v_refresh*/
                cfg->v_refresh = stream->timing.pix_clk_100hz * 100;
                cfg->v_refresh /= stream->timing.h_total;

diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index bf63da266a18cfbccaa01e2be951dd61d406c868..3b093b8699abd7e73403dba63c4760ed3cd64998 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -127,7 +127,7 @@ struct dm_pp_single_disp_config {
        uint32_t src_height;
        uint32_t src_width;
        uint32_t v_refresh;
-       uint32_t sym_clock; /* HDMI only */
+       uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only: normalized) */
        struct dc_link_settings link_settings; /* DP only */
 };
 

diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h b/drivers/gpu/drm/amd/include/dm_pp_interface.h
index acd1cef61b7c53013672d242d197d77b0a5bfde1..349544504c93cab0920d303f4c3a4a2f5c2aa1a3 100644 (file)
--- a/drivers/gpu/drm/amd/include/dm_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h
@@ -65,6 +65,7 @@ struct single_display_configuration {
        uint32_t view_resolution_cy;
        enum amd_pp_display_config_type displayconfigtype;
        uint32_t vertical_refresh; /* for active display */
+       uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only: normalized) */
 };
 
 #define MAX_NUM_DISPLAY 32