Modifications for 1.1.2:
======================================================================
+* The Big Rename: renamed 8240 ==> 824x to allow for easier
+ integration of 8245 and other 824x CPU's
+ Patch by Greg Allen <gallen@arlut.utexas.edu>, 26 Nov 2001
+
* Add "sleep" command
* Add loop constructs (for, while, until) to hush command interpreter
"
#########################################################################
-## MPC8240 Systems
+## MPC824x Systems
#########################################################################
-LIST_8240=" \
+LIST_824x=" \
CU824 \
MOUSSE \
Sandpoint8240 \
BAB750 \
"
-LIST_all="${LIST_8xx} ${LIST_8240} ${LIST_8260} \
+LIST_all="${LIST_8xx} ${LIST_824x} ${LIST_8260} \
${LIST_4xx} ${LIST_74xx} ${LIST_7xx}"
[ $# = 0 ] && set $LIST_all
for arg in $@
do
case "$arg" in
- 8xx|8240|8260|4xx|74xx) for target in `eval echo '$LIST_'${arg}`
+ 8xx|824x|8260|4xx|74xx) for target in `eval echo '$LIST_'${arg}`
do
build_target ${target}
done
echo "#include <config_$(@:_config=).h>" >config.h
#########################################################################
-## MPC8240 Systems
+## MPC824x Systems
#########################################################################
CU824_config: unconfig
cd ./include ; \
echo "ARCH = ppc" > config.mk ; \
echo "BOARD = cu824" >>config.mk ; \
- echo "CPU = mpc8240" >>config.mk ; \
+ echo "CPU = mpc824x" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
MOUSSE_config: unconfig
cd ./include ; \
echo "ARCH = ppc" > config.mk ; \
echo "BOARD = mousse" >>config.mk ; \
- echo "CPU = mpc8240" >>config.mk ; \
+ echo "CPU = mpc824x" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
Sandpoint8240_config: unconfig
cd ./include ; \
echo "ARCH = ppc" > config.mk ; \
echo "BOARD = sandpoint" >>config.mk ; \
- echo "CPU = mpc8240" >>config.mk ; \
+ echo "CPU = mpc824x" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
#########################################################################
- tools Tools to build S-Record or PPCBoot images, etc.
- cpu/mpc8xx Files specific to Motorola MPC8xx CPUs
-- cpu/mpc8240 Files specific to Motorola MPC8240 CPU
+- cpu/mpc824x Files specific to Motorola MPC824x CPUs
- cpu/mpc8260 Files specific to Motorola MPC8260 CPU
- cpu/mpc74xx Files specific to Motorola MPC74xx CPUs
- cpu/ppc4xx Files specific to IBM 4xx CPUs
- CPU Type: Define exactly one of
CONFIG_MPC823, CONFIG_MPC850, CONFIG_MPC855, CONFIG_MPC860
- or CONFIG_MPC8240, CONFIG_MPC8260
+ or CONFIG_MPC824X, CONFIG_MPC8260
or CONFIG_IOP480
or CONFIG_405GP
or CONFIG_MPC74xx
the lcd display every second with
a "rotator" |\-/|\-/
+- MPC824X Family Member (if CONFIG_MPC824X is defined)
+ Define exactly one of
+ CONFIG_MPC8240, CONFIG_MPC8245
+
- 8xx CPU Options: (if using an 8xx cpu)
Define one or more of
CONFIG_8xx_GCLK_FREQ - if get_gclk_freq() can not work e.g.
PPCBoot uses the following memory types:
- MPC8xx and MPC8260: IMMR (internal memory of the CPU)
- - MPC8240: data cache
+ - MPC824X: data cache
- CFG_INIT_DATA_OFFSET:
CFG_INIT_DATA_OFFSET) downward.
Note:
- On the MPC8240 (or other systems that use the data
+ On the MPC824X (or other systems that use the data
cache for initial memory) the address chosen for
CFG_INIT_RAM_ADDR is basically arbitrary - it must
point to an otherwise UNUSED address space between
FADS850SAR_config SPD823TS_config pcu_e_config
FADS860T_config SXNI855T_config rsdproto_config
FPS850L_config Sandpoint8240_config sbc8260_config
- GENIETV_config TQM823L_config PIP405_config
+ GENIETV_config TQM823L_config PIP405_config
Note: for some board special configuration names may exist; check if
additional information is available from the board vendor; for
*/
#include <ppcboot.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
#include <asm/processor.h>
#define BOARD_REV_REG 0xFE80002B
*addr = save[--i];
if (val != ~cnt) {
ulong new_bank0_end = cnt * sizeof(long) - 1;
- ulong mear1 = mpc8240_mpc107_getreg(MEAR1);
- ulong emear1 = mpc8240_mpc107_getreg(EMEAR1);
+ ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
+ ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc8240_mpc107_setreg(MEAR1, mear1);
- mpc8240_mpc107_setreg(EMEAR1, emear1);
+ mpc824x_mpc107_setreg(MEAR1, mear1);
+ mpc824x_mpc107_setreg(EMEAR1, emear1);
ret = cnt * sizeof(long);
goto Done;
#include <ppcboot.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
#include <net.h>
/* PCI Registers.
*/
#include <ppcboot.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
#include <asm/processor.h>
#if defined(CFG_ENV_IS_IN_FLASH)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8240/start.o (.text)
+ cpu/mpc824x/start.o (.text)
common/board.o (.text)
ppc/ppcstring.o (.text)
ppc/vsprintf.o (.text)
*/
#include <ppcboot.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
#include <asm/processor.h>
static char pll_to_bus_factor[] =
/* Table to convert pllratio to actual processor clock scaling factor (*10)
*/
-#ifdef CONFIG_MPC8240
+#ifdef CONFIG_MPC824X
short pllratio_to_factor[] = {
00, 00, 00, 10, 20, 20, 25, 00, 00, 00, 00, 00, 00, 00, 00, 00,
00, 00, 00, 10, 00, 00, 00, 45, 30, 00, 40, 00, 00, 00, 35, 00,
{
uint hid1 = mfspr(HID1);
-#ifdef CONFIG_MPC8240
+#ifdef CONFIG_MPC824X
- /* 5 bits for PLL ration on 8240
+ /* 5 bits for PLL ration on 824X
*/
hid1 = (hid1 >> (32-5)) & 0x1f;
#else
* DEC 21143 Ethernet driver.
*/
#include <ppcboot.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
#include <net.h>
#include "pci.h"
#include "mousse.h"
*/
#include <ppcboot.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
#include <asm/processor.h>
#include "mousse.h"
*/
/*
- * PCI Configuration space access support for MPC8240/MPC107 PCI Bridge
+ * PCI Configuration space access support for MPC824x/MPC107 PCI Bridge
*/
#include <ppcboot.h>
-#include "mpc8240.h"
+#include "mpc824x.h"
#include "pci.h"
#include "mousse.h"
uint8 retval = 0;
int retStat = ERROR;
- mpc8240_mpc107_write32 (CHRP_REG_ADDR,
+ mpc824x_mpc107_write32 (CHRP_REG_ADDR,
pci_config_bdf_pack (busNo, deviceNo, funcNo) |
(offset & 0xfc) | 0x80000000);
- retval = mpc8240_mpc107_read8 (CHRP_REG_DATA + (offset & 0x3));
+ retval = mpc824x_mpc107_read8 (CHRP_REG_DATA + (offset & 0x3));
retStat = OK;
*pData = retval;
return (retStat);
}
- mpc8240_mpc107_write32 (CHRP_REG_ADDR,
+ mpc824x_mpc107_write32 (CHRP_REG_ADDR,
pci_config_bdf_pack (busNo, deviceNo, funcNo) |
(offset & 0xfc) | 0x80000000);
- retval = mpc8240_mpc107_read16 (CHRP_REG_DATA + (offset & 0x2));
+ retval = mpc824x_mpc107_read16 (CHRP_REG_DATA + (offset & 0x2));
retStat = OK;
*pData = retval;
if (((offset & (int)0x3) > 0) ) {
return (retStat);
}
- mpc8240_mpc107_write32 (CHRP_REG_ADDR,
+ mpc824x_mpc107_write32 (CHRP_REG_ADDR,
pci_config_bdf_pack (busNo, deviceNo, funcNo) |
(offset & 0xfc) | 0x80000000);
- retval = mpc8240_mpc107_read32 (CHRP_REG_DATA);
+ retval = mpc824x_mpc107_read32 (CHRP_REG_DATA);
asm volatile ("eieio");
retStat = OK;
*pData = retval;
uint8 data) /* data written to the offset */
{
- mpc8240_mpc107_write32 (CHRP_REG_ADDR,
+ mpc824x_mpc107_write32 (CHRP_REG_ADDR,
pci_config_bdf_pack (busNo, deviceNo, funcNo) |
(offset & 0xfc) | 0x80000000);
- mpc8240_mpc107_write8 ((CHRP_REG_DATA + (offset & 0x3)), data);
+ mpc824x_mpc107_write8 ((CHRP_REG_DATA + (offset & 0x3)), data);
return OK;
}
return (ERROR);
}
- mpc8240_mpc107_write32 (CHRP_REG_ADDR,
+ mpc824x_mpc107_write32 (CHRP_REG_ADDR,
pci_config_bdf_pack (busNo, deviceNo, funcNo) |
(offset & 0xfc) | 0x80000000);
- mpc8240_mpc107_write16 ((CHRP_REG_DATA + (offset & 0x2)), data);
+ mpc824x_mpc107_write16 ((CHRP_REG_DATA + (offset & 0x2)), data);
return OK;
}
if (((offset & (int)0x3) > 0) ){
return (ERROR);
}
- mpc8240_mpc107_write32 (CHRP_REG_ADDR,
+ mpc824x_mpc107_write32 (CHRP_REG_ADDR,
pci_config_bdf_pack (busNo, deviceNo, funcNo) |
(offset & 0xfc) | 0x80000000);
- mpc8240_mpc107_write32 (CHRP_REG_DATA, data);
+ mpc824x_mpc107_write32 (CHRP_REG_DATA, data);
asm volatile ("eieio");
return OK;
}
int deviceNo = 0x0000001f;
int funcNo = 0x00000007;
- mpc8240_mpc107_write32 (CHRP_REG_ADDR,
+ mpc824x_mpc107_write32 (CHRP_REG_ADDR,
pci_config_bdf_pack (busNo, deviceNo, funcNo) |
0x80000000);
- mpc8240_mpc107_write32 (CHRP_REG_DATA, message);
+ mpc824x_mpc107_write32 (CHRP_REG_DATA, message);
return OK;
}
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#ifndef __MPC8240_PCI
-#define __MPC8240_PCI
+#ifndef __MPC824X_PCI
+#define __MPC824X_PCI
/*
- * PCI Configuration space Library and constants for MPC8240 based
+ * PCI Configuration space Library and constants for MPC824x based
* systems.
*/
unsigned int pci_size_bar(unsigned int, unsigned long mask);
#endif /* _ASMLANGUAGE */
-#endif /* __MPC8240_PCI */
+#endif /* __MPC824X_PCI */
.plt : { *(.plt) }
.text :
{
- cpu/mpc8240/start.o (.text)
- common/board.o (.text)
+ cpu/mpc824x/start.o (.text)
+ common/board.o (.text)
ppc/ppcstring.o (.text)
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
PROVIDE(_f_init_rom = .);
.init : {
- cpu/mpc8240/start.o (.text)
+ cpu/mpc824x/start.o (.text)
*(.init)
} > ram
_init_size = SIZEOF(.init);
.plt : { *(.plt) }
.text :
{
- cpu/mpc8240/start.o (.text)
+ cpu/mpc824x/start.o (.text)
common/board.o (.text)
ppc/ppcstring.o (.text)
ppc/vsprintf.o (.text)
*/
#include <ppcboot.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
#include <asm/processor.h>
/* Table to convert pllratio to actual processor clock scaling factor (*10)
*/
-#ifdef CONFIG_MPC8240
+#ifdef CONFIG_MPC824X
short pllratio_to_factor[] = {
00, 00, 00, 10, 20, 20, 25, 00, 00, 00, 00, 00, 00, 00, 00, 00,
00, 00, 00, 10, 00, 00, 00, 45, 60, 00, 40, 00, 00, 00, 35, 00,
{
uint hid1 = mfspr(HID1);
-#ifdef CONFIG_MPC8240
+#ifdef CONFIG_MPC824X
- /* 5 bits for PLL ration on 8240
+ /* 5 bits for PLL ration on 824x
*/
hid1 = (hid1 >> (32-5)) & 0x1f;
#else
#include <config.h>
#include <asm/processor.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
#include <ppc_asm.tmpl>
#if defined(USE_DINK32)
*/
#include <ppcboot.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
#include <asm/processor.h>
#include <asm/pci_io.h>
#include "w83c553f.h"
*/
#include <ppcboot.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
#include <asm/processor.h>
#include <config.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
#include "ns87308.h"
#include "ns16550.h" /* to configure the 87308's internal 16550's */
#include <asm/mc146818rtc.h> /* to configure 87308's RTC */
.plt : { *(.plt) }
.text :
{
- cpu/mpc8240/start.o (.text)
+ cpu/mpc824x/start.o (.text)
common/board.o (.text)
ppc/ppcstring.o (.text)
ppc/vsprintf.o (.text)
PROVIDE(_f_init_rom = .);
.init : {
- cpu/mpc8240/start.o (.text)
+ cpu/mpc824x/start.o (.text)
*(.init)
} > ram
_init_size = SIZEOF(.init);
*/
#include <ppcboot.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
int checkboard (void)
{
*/
#include <ppcboot.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
#include <asm/processor.h>
#include "speed.h"
* figure it out from the hardware book
*/
-#ifdef CONFIG_MPC8240
+#ifdef CONFIG_MPC824X
const unsigned char pllratio_to_factor[32] = {
0, 0, 0, 2, 4, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 2, 0, 0, 0, 9, 6, 0, 8, 0, 0, 0, 7, 0
{
uint hid1;
hid1 = mfspr(HID1);
- #ifdef CONFIG_MPC8240
- hid1 = (hid1 >> (32-5)) & 0x1f; /* 5 bits for PLL ration on 8240*/
+ #ifdef CONFIG_MPC824X
+ hid1 = (hid1 >> (32-5)) & 0x1f; /* 5 bits for PLL ration on 824x */
#else
hid1 = (hid1 >> (32-4)) & 0xf; /* 4 bits on everythings else*/
#endif
WATCHDOG_RESET();
-#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM))
+#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM)
icache_enable(); /* it's time to enable the instruction cache */
#endif
bedbug860_init();
#endif
-#if defined(CONFIG_MPC8240) || defined(CONFIG_MPC8260)
+#if defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260)
/* Processors that are 603e core based */
void bedbug603e_init( void );
PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8240 -ffixed-r2 -mstring -mcpu=603e -msoft-float
+PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float
* MA 02111-1307 USA
*/
-#include <mpc8240.h>
+#include <config.h>
+#include <mpc824x.h>
#include <ppcboot.h>
#include <command.h>
printf("MPC8240");
break;
+ case CPU_TYPE_8245:
+ printf("MPC8245");
+ break;
+
default:
return -1; /*not valid for this source*/
}
/* ------------------------------------------------------------------------- */
/*
- * The MPC8240 has an integrated PCI controller known as the MPC107.
+ * The MPC824x has an integrated PCI controller known as the MPC107.
* The following are MPC107 Bridge Controller and PCI Support functions
*
*/
* before returning to the caller.
*/
unsigned int
-mpc8240_mpc107_getreg(unsigned int regNum)
+mpc824x_mpc107_getreg(unsigned int regNum)
{
unsigned int temp;
/* swap the addr. to little endian */
*/
void
-mpc8240_mpc107_setreg(unsigned int regNum, unsigned int regVal)
+mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal)
{
/* swap the addr. to little endian */
*(volatile unsigned int *)CHRP_REG_ADDR = PCISWAP(regNum);
* Write a byte (8 bits) to a memory location.
*/
void
-mpc8240_mpc107_write8(unsigned int addr, unsigned char data)
+mpc824x_mpc107_write8(unsigned int addr, unsigned char data)
{
*(unsigned char*)addr = data;
__asm__("sync");
*/
void
-mpc8240_mpc107_write16(unsigned int address, unsigned short data)
+mpc824x_mpc107_write16(unsigned int address, unsigned short data)
{
*(volatile unsigned short *)address = BYTE_SWAP_16_BIT(data);
__asm__("sync");
*/
void
-mpc8240_mpc107_write32(unsigned int address, unsigned int data)
+mpc824x_mpc107_write32(unsigned int address, unsigned int data)
{
*(volatile unsigned int *)address = LONGSWAP(data);
__asm__("sync");
* Read a byte (8 bits) from a memory location.
*/
unsigned char
-mpc8240_mpc107_read8(unsigned int addr)
+mpc824x_mpc107_read8(unsigned int addr)
{
return *(volatile unsigned char*)addr;
}
* value before returning to the caller.
*/
unsigned short
-mpc8240_mpc107_read16(unsigned int address)
+mpc824x_mpc107_read16(unsigned int address)
{
unsigned short retVal;
retVal = BYTE_SWAP_16_BIT(*(unsigned short*)address);
* swap the value before returning to the caller.
*/
unsigned int
-mpc8240_mpc107_read32(unsigned int address)
+mpc824x_mpc107_read32(unsigned int address)
{
unsigned int retVal;
retVal = LONGSWAP(*(unsigned int *)address);
*/
unsigned int
-mpc8240_eummbar_read(unsigned int regNum)
+mpc824x_eummbar_read(unsigned int regNum)
{
unsigned int temp;
temp = *(volatile unsigned int *) (EUMBBAR_VAL + regNum) ;
*/
void
-mpc8240_eummbar_write(unsigned int regNum, unsigned int regVal)
+mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal)
{
*(volatile unsigned int *) (EUMBBAR_VAL + regNum) = PCISWAP(regVal);
return;
#include <ppcboot.h>
#include <asm/processor.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
/*
* Breath some life into the CPU...
CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
+#if defined(CONFIG_MPC8245)
+ CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set cache line size */
+ /* clear then set then clear the memory DLL */
+ CONFIG_READ_BYTE (AMBOR, val);
+ CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
+ CONFIG_WRITE_BYTE(AMBOR, val | 0x20);
+ CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
+#endif
+
CONFIG_READ_WORD(PICR1, val);
+#if defined(CONFIG_MPC8240)
CONFIG_WRITE_WORD( PICR1,
(val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) |
PIRC1_MSK | PICR1_PROC_TYPE_603E |
PICR1_FLASH_WR_EN | PICR1_MCP_EN |
PICR1_CF_DPARK | PICR1_EN_PCS |
PICR1_CF_APARK );
+#elif defined(CONFIG_MPC8245)
+ CONFIG_WRITE_WORD( PICR1,
+ (val & (PICR1_RCS0)) |
+ PICR1_PROC_TYPE_603E |
+ PICR1_FLASH_WR_EN | PICR1_MCP_EN |
+ PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
+ PICR1_DEC| PICR1_CF_APARK );
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+
CONFIG_READ_WORD(PICR2, val);
val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
CONFIG_WRITE_WORD(PICR2, val | PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS); /*1 wait state*/
#endif
CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT);
-
+#if defined(CONFIG_MPC8240)
CONFIG_WRITE_WORD(MCCR3,
(((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
(CFG_REFREC << MCCR3_REFREC_SHIFT) |
(CFG_RDLAT << MCCR3_RDLAT_SHIFT));
+#elif defined(CONFIG_MPC8245)
+ CONFIG_WRITE_WORD(MCCR3,
+ (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
+ (CFG_REFREC << MCCR3_REFREC_SHIFT));
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
-#ifdef CONFIG_CU824
- CONFIG_WRITE_WORD(MCCR4,
+/* this is gross. We think these should all be the same, and various boards
+ * should define CFG_ACTORW to 0 if they don't want to set it, or even, if
+ * its not set, we define it to zero in this file
+ */
+#if defined(CONFIG_CU824)
+ CONFIG_WRITE_WORD(MCCR4,
(CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
(CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
MCCR4_BIT21 |
(CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
(((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
- CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
+ CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
(CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
(((CFG_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
-#else
- CONFIG_WRITE_WORD(MCCR4,
+#elif defined(CONFIG_MPC8240)
+ CONFIG_WRITE_WORD(MCCR4,
(CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
(CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
MCCR4_BIT21 |
(CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
- (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) | (CFG_SDMODE_BURSTLEN))
- <<MCCR4_SDMODE_SHIFT) |
- ((CFG_BSTOPRE & 0x03c0) <<MCCR4_BSTOPRE6TO9_SHIFT ));
+ (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
+ (CFG_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
+ (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
+#elif defined(CONFIG_MPC8245)
+ CONFIG_WRITE_WORD(MCCR4,
+ (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
+ (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
+ MCCR4_EXTROM | MCCR4_REGDIMM |
+ (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
+ ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
+ (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
+ (CFG_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
+ (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
+ (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
CONFIG_WRITE_WORD(MSAR1,
(CFG_BANK6_ENABLE << 6) |
(CFG_BANK7_ENABLE << 7));
+#ifdef CONFIG_MPC8245
+ CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX)
+#endif
+
/* ! Wait 200us before initialize other registers */
/*FIXME: write a decent udelay wait */
__asm__ __volatile__(
{BMC_BASE+0x8, "MPC107 Revision"},
{BMC_BASE+0xC, "MPC107 Cache Line Size"},
{BMC_BASE+0x10, "MPC107 LMBAR"},
- {BMC_BASE+0x14, "MPC8240 PCSR"},
- {BMC_BASE+0xA8, "MPC8240 PICR1"},
- {BMC_BASE+0xAC, "MPC8240 PICR2"},
- {BMC_BASE+0x46, "MPC8240 PACR"},
- {BMC_BASE+0x310, "MPC8240 ITWR"},
- {BMC_BASE+0x300, "MPC8240 OMBAR"},
- {BMC_BASE+0x308, "MPC8240 OTWR"},
+ {BMC_BASE+0x14, "MPC824x PCSR"},
+ {BMC_BASE+0xA8, "MPC824x PICR1"},
+ {BMC_BASE+0xAC, "MPC824x PICR2"},
+ {BMC_BASE+0x46, "MPC824x PACR"},
+ {BMC_BASE+0x310, "MPC824x ITWR"},
+ {BMC_BASE+0x300, "MPC824x OMBAR"},
+ {BMC_BASE+0x308, "MPC824x OTWR"},
{BMC_BASE+0x14, "MPC107 Peripheral Control and Status Register"},
{BMC_BASE+0x78, "MPC107 EUMBAR"},
{BMC_BASE+0xC0, "MPC107 Processor Bus Error Status"},
* This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can
* be accessed.
*/
- mpc8240_mpc107_setreg(EUMBBAR, EUMBBAR_VAL);
+#ifdef CONFIG_MPC8240 /* only on MPC8240 */
+ mpc824x_mpc107_setreg(EUMBBAR, EUMBBAR_VAL);
/* MOT/SPS: Issue #10002, PCI (FD Alias enable)*/
- mpc8240_mpc107_setreg(AMBOR, 0x000000C0);
+ mpc824x_mpc107_setreg(AMBOR, 0x000000C0);
+#endif
#ifdef INCLUDE_MPC107_REPORT
- /* Check MPC8240 PCI Device and Vendor ID */
- while((tmp = mpc8240_mpc107_getreg(BMC_BASE)) != 0x31057){
+ /* Check MPC824x PCI Device and Vendor ID */
+ while((tmp = mpc824x_mpc107_getreg(BMC_BASE)) != 0x31057){
printf(" MPC107: offset=0x%x, val = 0x%x\n", BMC_BASE, tmp);
}
for( i = 0; i < N_MPC107_Regs; i++){
printf(" 0x%x/%s = 0x%x\n", MPC107Regs[i].iobase,
- MPC107Regs[i].desc, mpc8240_mpc107_getreg(MPC107Regs[i].iobase));
+ MPC107Regs[i].desc, mpc824x_mpc107_getreg(MPC107Regs[i].iobase));
}
printf("IBAT0L = 0x%08X\n", mfspr(IBAT0L));
* copyright @ motorola, 1999
*
*************************************************/
-#include <mpc8240.h>
+#include <mpc824x.h>
#include <ppcboot.h>
#include "epic.h"
*/
#include <ppcboot.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
#include <asm/processor.h>
#include <asm/pci_io.h>
#include <commproc.h>
* address and (s)dram will be positioned at address 0
*/
#include <config.h>
-#include <mpc8240.h>
+#include <mpc824x.h>
#include "version.h"
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <bedbug/regs.h>
#include <bedbug/ppc.h>
-#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && (defined(CONFIG_MPC8240) || defined(CONFIG_MPC8260))
+#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && (defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260))
#define MAX_BREAK_POINTS 1
* (easy to change)
*/
+#define CONFIG_MPC824X 1
#define CONFIG_MPC8240 1
#define CONFIG_CU824 1
* (easy to change)
*/
+#define CONFIG_MPC824X 1
#define CONFIG_MPC8240 1
#define CONFIG_MOUSSE 1
#define CFG_ADDR_MAP_B 1
* (easy to change)
*/
+#define CONFIG_MPC824X 1
#define CONFIG_MPC8240 1
#define CONFIG_SANDPOINT 1
#define USE_DINK32 1
* MA 02111-1307 USA
*/
-#ifndef __MPC8240_H__
-#define __MPC8240_H__
+#ifndef __MPC824X_H__
+#define __MPC824X_H__
+#include <config.h>
/* CPU Types */
#define CPU_TYPE_601 0x01 /* PPC 601 CPU */
#define CPU_TYPE_604R 0x0a /* PPC 604r CPU */
#define CPU_TYPE_750 0x08 /* PPC 750 CPU */
#define CPU_TYPE_8240 0x81 /* PPC 8240 CPU */
-#define _CACHE_ALIGN_SIZE 32 /* cache line size */
+#define CPU_TYPE_8245 0x8081 /* PPC 8245 CPU */
+#define _CACHE_ALIGN_SIZE 32 /* cache line size */
/* spr976 - DMISS data tlb miss address register
* spr977 - DCMP data tlb miss compare register
#define PMCR2 0x80000072 /* Power management config. 2 */
#define ODCR 0x80000073 /* Output Driver Control Register */
#define CLKDCR 0x80000074 /* CLK Driver Control Register */
+#ifdef CONFIG_MPC8245
+#define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */
+#define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */
+#endif
#define EUMBBAR 0x80000078 /* Embedded Utilities Memory Block Base Address Register */
#define EUMBBAR_VAL 0x80500000 /* PCI Relocation offset for EUMB region */
#define EUMBSIZE 0x00100000 /* Size of EUMB region */
#define PICR1_CF_APARK 0x00000008
#define PICR1_LE_MODE 0x00000020
#define PICR1_ST_GATH_EN 0x00000040
+#if defined(CONFIG_MPC8240)
#define PICR1_EN_PCS 0x00000080 /* according to dink code, sets the 8240 to handle pci config space */
+#elif defined(CONFIG_MPC8241) || defined(CONFIG_MPC8245)
+#define PICR1_NO_BUSW_CK 0x00000080 /* no bus width check for flash writes */
+#define PICR1_DEC 0x00000100 /* Time Base enable on 8245/8241 */
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
#define PICR1_CF_DPARK 0x00000200
#define PICR1_MCP_EN 0x00000800
#define PICR1_FLASH_WR_EN 0x00001000
+#ifdef CONFIG_MPC8240
#define PICR1_ADDRESS_MAP 0x00010000
+#define PIRC1_MSK 0xff000000
+#endif
#define PICR1_PROC_TYPE_MSK 0x00060000
#define PICR1_PROC_TYPE_603E 0x00040000
#define PICR1_RCS0 0x00100000
-#define PIRC1_MSK 0xff000000
#define PICR2_CF_SNOOP_WS_MASK 0x000c0000
#define PICR2_CF_SNOOP_WS_0WS 0x00000000
#define MCCR1_ROMNAL_MSK 0xf0000000
#define MCCR1_ROMFAL_SHIFT 23
#define MCCR1_ROMFAL_MSK 0x0f800000
+#define MCCR1_DBUS_SIZE0TO1_SHIFT 21
#define MCCR1_BURST 0x00100000
#define MCCR1_MEMGO 0x00080000
#define MCCR1_SREN 0x00040000
+#if defined(CONFIG_MPC8240)
#define MCCR1_RAM_TYPE 0x00020000
+#elif defined(CONFIG_MPC8245)
+#define MCCR1_SDRAM_EN 0x00020000
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
#define MCCR1_PCKEN 0x00010000
#define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000
#define MCCR2_INLINE_PAR_NOT_ECC 0x00100000
#define MCCR2_WRITE_PARITY_CHK 0x00080000
#define MCCR2_INLFRD_PARECC_CHK_EN 0x00040000
+#ifdef CONFIG_MPC8240
#define MCCR2_ECC_EN 0x00020000
#define MCCR2_EDO 0x00010000
+#endif
#define MCCR2_REFINT_MSK 0x0000fffc
#define MCCR2_REFINT_SHIFT 2
#define MCCR2_RSV_PG 0x00000002
#define MCCR3_BSTOPRE2TO5_SHIFT 28
#define MCCR3_REFREC_MSK 0x0f000000
#define MCCR3_REFREC_SHIFT 24
+#ifdef CONFIG_MPC8240
#define MCCR3_RDLAT_MSK 0x00f00000
#define MCCR3_RDLAT_SHIFT 20
#define MCCR3_CPX 0x00010000
#define MCCR3_RCD2_SHIFT 3
#define MCCR3_RP1_MSK 0x00000007
#define MCCR3_RP1_SHIFT 0
+#endif
#define MCCR4_PRETOACT_MSK 0xf0000000
#define MCCR4_PRETOACT_SHIFT 28
#define MCCR4_ACTTOPRE_SHIFT 24
#define MCCR4_WMODE 0x00800000
#define MCCR4_INLINE 0x00400000
+#if defined(CONFIG_MPC8240)
#define MCCR4_BIT21 0x00200000 /* this include cos DINK code sets it- unknown function*/
+#elif defined(CONFIG_MPC8245)
+#define MCCR4_EXTROM 0x00200000 /* enables Extended ROM space */
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
#define MCCR4_REGISTERED 0x00100000
#define MCCR4_BSTOPRE0TO1_MSK 0x000c0000 /*BSTOPRE[0-1]*/
#define MCCR4_BSTOPRE0TO1_SHIFT 18
#define MCCR4_ACTTORW_SHIFT 4
#define MCCR4_BSTOPRE6TO9_MSK 0x0000000f /*BSTOPRE[6-9]*/
#define MCCR4_BSTOPRE6TO9_SHIFT 0
+#define MCCR4_DBUS_SIZE2_SHIFT 17
#define MICR_ADDR_MASK 0x0ff00000
#define MICR_ADDR_SHIFT 20
* MPC107 Support
*
*/
-unsigned int mpc8240_mpc107_getreg(unsigned int regNum);
-void mpc8240_mpc107_setreg(unsigned int regNum, unsigned int regVal);
-void mpc8240_mpc107_write8(unsigned int address, unsigned char data);
-void mpc8240_mpc107_write16(unsigned int address, unsigned short data);
-void mpc8240_mpc107_write32(unsigned int address, unsigned int data);
-unsigned char mpc8240_mpc107_read8(unsigned int address);
-unsigned short mpc8240_mpc107_read16(unsigned int address);
-unsigned int mpc8240_mpc107_read32(unsigned int address);
-unsigned int mpc8240_eummbar_read(unsigned int regNum);
-void mpc8240_eummbar_write(unsigned int regNum, unsigned int regVal);
+unsigned int mpc824x_mpc107_getreg(unsigned int regNum);
+void mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal);
+void mpc824x_mpc107_write8(unsigned int address, unsigned char data);
+void mpc824x_mpc107_write16(unsigned int address, unsigned short data);
+void mpc824x_mpc107_write32(unsigned int address, unsigned int data);
+unsigned char mpc824x_mpc107_read8(unsigned int address);
+unsigned short mpc824x_mpc107_read16(unsigned int address);
+unsigned int mpc824x_mpc107_read32(unsigned int address);
+unsigned int mpc824x_eummbar_read(unsigned int regNum);
+void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal);
unsigned long get_gclk_freq(void);
#endif /* __ASSEMBLY__ */
-#endif /* __MPC8240_H__ */
+#endif /* __MPC824X_H__ */
#define r31 31
-#if defined(CONFIG_8xx) || defined(CONFIG_MPC8240)
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC824X)
/* Some special registers */
#define LCTRL2 157 /* Load/Store Support (37-41) */
#define ICTRL 158
-#endif /* CONFIG_8xx, CONFIG_MPC8240 */
+#endif /* CONFIG_8xx, CONFIG_MPC824X */
#if defined(CONFIG_8xx)