drm/amd/display: Add Interface to set FIFO ERRDET SW Override

[WHY]
HW has handed down a new sequence which requires access to the FIFO
ERRDET SW Override register.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
index 8774406120fc1c5ce8297c906880ca276f29af30..5679983158e24d719a689f217b206ac70a3d1c39 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
@@ -96,6 +96,15 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg,
        return;
 }
 
+void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
+               bool en)
+{
+       struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+       REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL,
+                       DCCG_FIFO_ERRDET_OVR_EN, en ? 1 : 0);
+}
+
 void dccg2_init(struct dccg *dccg)
 {
 }
@@ -103,6 +112,7 @@ void dccg2_init(struct dccg *dccg)
 static const struct dccg_funcs dccg2_funcs = {
        .update_dpp_dto = dccg2_update_dpp_dto,
        .get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+       .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
        .dccg_init = dccg2_init
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index e5aa2da3176da45c37134f0a24024ef46305b03d..5203ee0a65aa047603548e7247ec627c06cb68a2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -34,7 +34,8 @@
        DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
        DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
        DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
-       SR(REFCLK_CNTL)
+       SR(REFCLK_CNTL),\
+       SR(DISPCLK_FREQ_CHANGE_CNTL)
 
 #define DCCG_REG_LIST_DCN2() \
        DCCG_COMMON_REG_LIST_DCN_BASE(),\
@@ -59,7 +60,16 @@
        DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
        DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
        DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
-       DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
+       DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\
+       DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
+       DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
+       DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
+       DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
+       DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
+       DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
+       DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
+       DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh)
+
 
 #define DCCG_MASK_SH_LIST_DCN2(mask_sh) \
        DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
@@ -74,7 +84,16 @@
        type DPPCLK_DTO_ENABLE[6];\
        type DPPCLK_DTO_DB_EN[6];\
        type REFCLK_CLOCK_EN;\
-       type REFCLK_SRC_SEL;
+       type REFCLK_SRC_SEL;\
+       type DISPCLK_STEP_DELAY;\
+       type DISPCLK_STEP_SIZE;\
+       type DISPCLK_FREQ_RAMP_DONE;\
+       type DISPCLK_MAX_ERRDET_CYCLES;\
+       type DCCG_FIFO_ERRDET_RESET;\
+       type DCCG_FIFO_ERRDET_STATE;\
+       type DCCG_FIFO_ERRDET_OVR_EN;\
+       type DISPCLK_CHG_FWD_CORR_DISABLE;\
+       type DISPCLK_FREQ_CHANGE_CNTL;
 
 #define DCCG3_REG_FIELD_LIST(type) \
        type PHYASYMCLK_FORCE_EN;\
@@ -137,6 +156,7 @@ struct dccg_registers {
        uint32_t DPPCLK_DTO_CTRL;
        uint32_t DPPCLK_DTO_PARAM[6];
        uint32_t REFCLK_CNTL;
+       uint32_t DISPCLK_FREQ_CHANGE_CNTL;
        uint32_t HDMICHARCLK_CLOCK_CNTL[6];
        uint32_t PHYASYMCLK_CLOCK_CNTL;
        uint32_t PHYBSYMCLK_CLOCK_CNTL;
@@ -171,6 +191,9 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg,
                unsigned int xtalin_freq_inKhz,
                unsigned int *dccg_ref_freq_inKhz);
 
+void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
+               bool en);
+
 void dccg2_init(struct dccg *dccg);
 
 struct dccg *dccg2_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c
index 60cf3ff68cb081945dd87c3343ff870b54432fa3..6e1befbb44588238c7a87aadbe11a6aea42076a2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c
@@ -100,6 +100,7 @@ void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
 static const struct dccg_funcs dccg21_funcs = {
        .update_dpp_dto = dccg21_update_dpp_dto,
        .get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+       .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
        .dccg_init = dccg2_init
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c
index b822a13e40cefd9ced16b9e60418885e5d58518e..570f6eacd4e4e84833f909da0de8f6809fd9ce8e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c
@@ -46,6 +46,7 @@
 static const struct dccg_funcs dccg3_funcs = {
        .update_dpp_dto = dccg2_update_dpp_dto,
        .get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+       .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
        .dccg_init = dccg2_init
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c
index 420da414929c1676740c42698f4e93dc6f23b1ab..6e6af02b38f9ebfa890814f980680dce4557f033 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c
@@ -45,6 +45,7 @@
 static const struct dccg_funcs dccg301_funcs = {
        .update_dpp_dto = dccg2_update_dpp_dto,
        .get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+       .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
        .dccg_init = dccg2_init
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index f7aa703e3175a2c67bc048e312c0924adb4d2855..d3d7c338e491bd2cb22bbdcb691f860e80179b07 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -76,6 +76,8 @@ struct dccg_funcs {
        void (*get_dccg_ref_freq)(struct dccg *dccg,
                        unsigned int xtalin_freq_inKhz,
                        unsigned int *dccg_ref_freq_inKhz);
+       void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
+                       bool en);
        void (*dccg_init)(struct dccg *dccg);
 #if defined(CONFIG_DRM_AMD_DC_DCN3_1)