cpufreq/amd-pstate: Replace all AMD_CPPC_* macros with masks

Bitfield masks are easier to follow and less error prone.

Reviewed-by: Dhananjay Ugwekar <dhananjay.ugwekar@amd.com>
Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 72765b2fe0d874b498fb77b90e2f121890ca49f0..fc2634cc48fd1f72305d49607d3090c65e3f2f52 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -701,15 +701,17 @@
 #define MSR_AMD_CPPC_REQ               0xc00102b3
 #define MSR_AMD_CPPC_STATUS            0xc00102b4
 
-#define AMD_CPPC_LOWEST_PERF(x)                (((x) >> 0) & 0xff)
-#define AMD_CPPC_LOWNONLIN_PERF(x)     (((x) >> 8) & 0xff)
-#define AMD_CPPC_NOMINAL_PERF(x)       (((x) >> 16) & 0xff)
-#define AMD_CPPC_HIGHEST_PERF(x)       (((x) >> 24) & 0xff)
-
-#define AMD_CPPC_MAX_PERF(x)           (((x) & 0xff) << 0)
-#define AMD_CPPC_MIN_PERF(x)           (((x) & 0xff) << 8)
-#define AMD_CPPC_DES_PERF(x)           (((x) & 0xff) << 16)
-#define AMD_CPPC_ENERGY_PERF_PREF(x)   (((x) & 0xff) << 24)
+/* Masks for use with MSR_AMD_CPPC_CAP1 */
+#define AMD_CPPC_LOWEST_PERF_MASK      GENMASK(7, 0)
+#define AMD_CPPC_LOWNONLIN_PERF_MASK   GENMASK(15, 8)
+#define AMD_CPPC_NOMINAL_PERF_MASK     GENMASK(23, 16)
+#define AMD_CPPC_HIGHEST_PERF_MASK     GENMASK(31, 24)
+
+/* Masks for use with MSR_AMD_CPPC_REQ */
+#define AMD_CPPC_MAX_PERF_MASK         GENMASK(7, 0)
+#define AMD_CPPC_MIN_PERF_MASK         GENMASK(15, 8)
+#define AMD_CPPC_DES_PERF_MASK         GENMASK(23, 16)
+#define AMD_CPPC_EPP_PERF_MASK         GENMASK(31, 24)
 
 /* AMD Performance Counter Global Status and Control MSRs */
 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS      0xc0000300

diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c
index d745dd586303ccc85e21cd78294e1db4e0b4d59b..77bfb846490c07bb2bee9ac789423b486fbe5176 100644 (file)
--- a/arch/x86/kernel/acpi/cppc.c
+++ b/arch/x86/kernel/acpi/cppc.c
@@ -4,6 +4,8 @@
  * Copyright (c) 2016, Intel Corporation.
  */
 
+#include <linux/bitfield.h>
+
 #include <acpi/cppc_acpi.h>
 #include <asm/msr.h>
 #include <asm/processor.h>
@@ -149,7 +151,7 @@ int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf)
                if (ret)
                        goto out;
 
-               val = AMD_CPPC_HIGHEST_PERF(val);
+               val = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, val);
        } else {
                ret = cppc_get_highest_perf(cpu, &val);
                if (ret)

diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c
index edc1475989e3da2853c632733452485cbf8027d0..e671bc7d155082a8c04a5faa743b64a858c58146 100644 (file)
--- a/drivers/cpufreq/amd-pstate-ut.c
+++ b/drivers/cpufreq/amd-pstate-ut.c
@@ -22,6 +22,7 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
+#include <linux/bitfield.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
@@ -142,10 +143,10 @@ static int amd_pstate_ut_check_perf(u32 index)
                                return ret;
                        }
 
-                       highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
-                       nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1);
-                       lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1);
-                       lowest_perf = AMD_CPPC_LOWEST_PERF(cap1);
+                       highest_perf = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1);
+                       nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1);
+                       lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1);
+                       lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
                }
 
                cur_perf = READ_ONCE(cpudata->perf);

diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 6f1a3056bcbd941477327a77814c25eb86ac2043..5c439b14caae385805ae1d844eb1cb2f1f965b23 100644 (file)
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -89,11 +89,6 @@ static bool cppc_enabled;
 static bool amd_pstate_prefcore = true;
 static struct quirk_entry *quirks;
 
-#define AMD_CPPC_MAX_PERF_MASK         GENMASK(7, 0)
-#define AMD_CPPC_MIN_PERF_MASK         GENMASK(15, 8)
-#define AMD_CPPC_DES_PERF_MASK         GENMASK(23, 16)
-#define AMD_CPPC_EPP_PERF_MASK         GENMASK(31, 24)
-
 /*
  * AMD Energy Preference Performance (EPP)
  * The EPP is used in the CCLK DPM controller to drive
@@ -439,12 +434,13 @@ static int msr_init_perf(struct amd_cpudata *cpudata)
 
        perf.highest_perf = numerator;
        perf.max_limit_perf = numerator;
-       perf.min_limit_perf = AMD_CPPC_LOWEST_PERF(cap1);
-       perf.nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1);
-       perf.lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1);
-       perf.lowest_perf = AMD_CPPC_LOWEST_PERF(cap1);
+       perf.min_limit_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
+       perf.nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1);
+       perf.lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1);
+       perf.lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
        WRITE_ONCE(cpudata->perf, perf);
-       WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1));
+       WRITE_ONCE(cpudata->prefcore_ranking, FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1));
+
        return 0;
 }