clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64

A64 has rotation core which needs clocks and reset. Because there is no
appropriate structures available, make a separate, A64 specific
structures.

Fixes: cf4881c12935 ("clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 2478ae314d0f0a2e145a7b0a14bcff769d6c820e..c6220be8e2056f9c521fe82514e2a1fc87d20248 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -108,6 +108,24 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = {
        &wb_div_clk.common,
 };
 
+static struct ccu_common *sun50i_a64_de2_clks[] = {
+       &mixer0_clk.common,
+       &mixer1_clk.common,
+       &wb_clk.common,
+
+       &bus_mixer0_clk.common,
+       &bus_mixer1_clk.common,
+       &bus_wb_clk.common,
+
+       &mixer0_div_clk.common,
+       &mixer1_div_clk.common,
+       &wb_div_clk.common,
+
+       &bus_rot_clk.common,
+       &rot_clk.common,
+       &rot_div_clk.common,
+};
+
 static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
        .hws    = {
                [CLK_MIXER0]            = &mixer0_clk.common.hw,
@@ -156,6 +174,26 @@ static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
        .num    = CLK_NUMBER_WITHOUT_ROT,
 };
 
+static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
+       .hws    = {
+               [CLK_MIXER0]            = &mixer0_clk.common.hw,
+               [CLK_MIXER1]            = &mixer1_clk.common.hw,
+               [CLK_WB]                = &wb_clk.common.hw,
+               [CLK_ROT]               = &rot_clk.common.hw,
+
+               [CLK_BUS_MIXER0]        = &bus_mixer0_clk.common.hw,
+               [CLK_BUS_MIXER1]        = &bus_mixer1_clk.common.hw,
+               [CLK_BUS_WB]            = &bus_wb_clk.common.hw,
+               [CLK_BUS_ROT]           = &bus_rot_clk.common.hw,
+
+               [CLK_MIXER0_DIV]        = &mixer0_div_clk.common.hw,
+               [CLK_MIXER1_DIV]        = &mixer1_div_clk.common.hw,
+               [CLK_WB_DIV]            = &wb_div_clk.common.hw,
+               [CLK_ROT_DIV]           = &rot_div_clk.common.hw,
+       },
+       .num    = CLK_NUMBER_WITH_ROT,
+};
+
 static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
        .hws    = {
                [CLK_MIXER0]            = &mixer0_clk.common.hw,
@@ -190,6 +228,7 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = {
        [RST_MIXER0]    = { 0x08, BIT(0) },
        [RST_MIXER1]    = { 0x08, BIT(1) },
        [RST_WB]        = { 0x08, BIT(2) },
+       [RST_ROT]       = { 0x08, BIT(3) },
 };
 
 static struct ccu_reset_map sun50i_h5_de2_resets[] = {
@@ -226,10 +265,10 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
 };
 
 static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
-       .ccu_clks       = sun8i_h3_de2_clks,
-       .num_ccu_clks   = ARRAY_SIZE(sun8i_h3_de2_clks),
+       .ccu_clks       = sun50i_a64_de2_clks,
+       .num_ccu_clks   = ARRAY_SIZE(sun50i_a64_de2_clks),
 
-       .hw_clks        = &sun8i_h3_de2_hw_clks,
+       .hw_clks        = &sun50i_a64_de2_hw_clks,
 
        .resets         = sun50i_a64_de2_resets,
        .num_resets     = ARRAY_SIZE(sun50i_a64_de2_resets),