Merge tag 'iommu-updates-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro...

Pull IOMMU updates from Joerg Roedel:

 - updates for the Exynos IOMMU driver to make use of default domains
   and to add support for the SYSMMU v5

 - new Mediatek IOMMU driver

 - support for the ARMv7 short descriptor format in the io-pgtable code

 - default domain support for the ARM SMMU

 - couple of other small fixes all over the place

* tag 'iommu-updates-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (41 commits)
  iommu/ipmmu-vmsa: Add r8a7795 DT binding
  iommu/mediatek: Check for NULL instead of IS_ERR()
  iommu/io-pgtable-armv7s: Fix kmem_cache_alloc() flags
  iommu/mediatek: Fix handling of of_count_phandle_with_args result
  iommu/dma: Fix NEED_SG_DMA_LENGTH dependency
  iommu/mediatek: Mark PM functions as __maybe_unused
  iommu/mediatek: Select ARM_DMA_USE_IOMMU
  iommu/exynos: Use proper readl/writel register interface
  iommu/exynos: Pointers are nto physical addresses
  dts: mt8173: Add iommu/smi nodes for mt8173
  iommu/mediatek: Add mt8173 IOMMU driver
  memory: mediatek: Add SMI driver
  dt-bindings: mediatek: Add smi dts binding
  dt-bindings: iommu: Add binding for mediatek IOMMU
  iommu/ipmmu-vmsa: Use ARCH_RENESAS
  iommu/exynos: Support multiple attach_device calls
  iommu/exynos: Add Maintainers entry for Exynos SYSMMU driver
  iommu/exynos: Add support for v5 SYSMMU
  iommu/exynos: Update device tree documentation
  iommu/exynos: Add support for SYSMMU controller with bogus version reg
  ...

diff --cc MAINTAINERS
Simple merge

diff --cc arch/arm64/boot/dts/mediatek/mt8173.dtsi
index f4bd3c9182ad3b4f441281304bdafae2f7822193,804881181fcc41f6396c1d580bb2a0377857a2e3..eab7efc2302d135a0aaec2a529ee200d95259315
--- 1/arch/arm64/boot/dts/mediatek/mt8173.dtsi
--- 2/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@@ -277,11 -278,17 +278,22 @@@
                        reg = <0 0x10200620 0 0x20>;
                };
  
+               iommu: iommu@10205000 {
+                       compatible = "mediatek,mt8173-m4u";
+                       reg = <0 0x10205000 0 0x1000>;
+                       interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&infracfg CLK_INFRA_M4U>;
+                       clock-names = "bclk";
+                       mediatek,larbs = <&larb0 &larb1 &larb2
+                                         &larb3 &larb4 &larb5>;
+                       #iommu-cells = <1>;
+               };
+ 
 +              efuse: efuse@10206000 {
 +                      compatible = "mediatek,mt8173-efuse";
 +                      reg = <0 0x10206000 0 0x1000>;
 +              };
 +
                apmixedsys: clock-controller@10209000 {
                        compatible = "mediatek,mt8173-apmixedsys";
                        reg = <0 0x10209000 0 0x1000>;