spi: spi_amd: Performance Optimization Patch Series

Merge series from Raju Rangoju <Raju.Rangoju@amd.com>:

AMD SPI controller’s index mode performance is constrained by the
hardware limitation of the FIFO queue length. This patch series introduces
optimizations to the spi_amd driver, aiming to maximize throughput and
enhance overall performance. The changes includes,

- Enable SPI dual and quad I/O modes and update SPI-MEM support function to
reflect AMD SPI0 hardware capabilities.
- Utilize efficient kernel APIs to streamline SPI I/O operations for
enhanced performance.
- Refine the set tx/rx count functions to optimize SPI I/O throughput.
- Minimize the number of data read calls by efficiently retrieving data
from FIFO queues, improving SPI I/O efficiency.
- Add changes to support AMD HID2 SPI controller and update SPI-MEM support
function to reflect AMD HID2 hardware capabilities.
- Add changes to set SPI controller address mode before initiating the
commands
- Add changes to implement HIDDMA read operation support for HID2 SPI
controller