tg3: Revise 5719 internal FIFO overflow solution

Commit cf79003d598b1f82a4caa0564107283b4f560e14, entitled
"tg3: Fix 5719 internal FIFO overflow problem", proposed a way to solve
an internal FIFO overflow problem.  We have since discovered a slightly
better way to solve the problem.  This patch changes the code so that
the problem is contained closer to the problem source.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 7841a8f69998d5351bad0745350edcfa65972208..b944cc64a40913663dc77d1620f73ae46a0016e7 100644 (file)
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -8227,8 +8227,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
            (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
                val = tr32(TG3_RDMA_RSRVCTRL_REG);
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
-                       val &= ~TG3_RDMA_RSRVCTRL_TXMRGN_MASK;
-                       val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B;
+                       val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
+                                TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
+                                TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
+                       val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
+                              TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
+                              TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
                }
                tw32(TG3_RDMA_RSRVCTRL_REG,
                     val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
@@ -13394,42 +13398,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
 
                tp->pcie_readrq = 4096;
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
-                       u16 word;
-
-                       pci_read_config_word(tp->pdev,
-                                            tp->pcie_cap + PCI_EXP_LNKSTA,
-                                            &word);
-                       switch (word & PCI_EXP_LNKSTA_CLS) {
-                       case PCI_EXP_LNKSTA_CLS_2_5GB:
-                               word &= PCI_EXP_LNKSTA_NLW;
-                               word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
-                               switch (word) {
-                               case 2:
-                                       tp->pcie_readrq = 2048;
-                                       break;
-                               case 4:
-                                       tp->pcie_readrq = 1024;
-                                       break;
-                               }
-                               break;
-
-                       case PCI_EXP_LNKSTA_CLS_5_0GB:
-                               word &= PCI_EXP_LNKSTA_NLW;
-                               word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
-                               switch (word) {
-                               case 1:
-                                       tp->pcie_readrq = 2048;
-                                       break;
-                               case 2:
-                                       tp->pcie_readrq = 1024;
-                                       break;
-                               case 4:
-                                       tp->pcie_readrq = 512;
-                                       break;
-                               }
-                       }
-               }
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
+                       tp->pcie_readrq = 2048;
 
                pcie_set_readrq(tp->pdev, tp->pcie_readrq);
 

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index d62c8d937c820cf3a124a2250a351156b49a84c6..0a0987aeb32e2d6202c4ea8e6f2f08ff64cb2d2d 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1333,6 +1333,10 @@
 
 #define TG3_RDMA_RSRVCTRL_REG          0x00004900
 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX         0x00000004
+#define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K         0x00000c00
+#define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK         0x00000ff0
+#define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K         0x000c0000
+#define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK         0x000ff000
 #define TG3_RDMA_RSRVCTRL_TXMRGN_320B   0x28000000
 #define TG3_RDMA_RSRVCTRL_TXMRGN_MASK   0xffe00000
 /* 0x4904 --> 0x4910 unused */