intel_display_param_named_unsafe(enable_psr, int, 0400,
        "Enable PSR "
-       "(0=disabled, 1=enable up to PSR1 and Panel Replay full frame update, "
-       "2=enable up to PSR2 and Panel Replay Selective Update) "
+       "(0=disabled, 1=enable up to PSR1, 2=enable up to PSR2) "
        "Default: -1 (use per-chip default)");
 
 intel_display_param_named(psr_safest_params, bool, 0400,
 
        }
 }
 
+static bool panel_replay_global_enabled(struct intel_dp *intel_dp)
+{
+       struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+       if (i915->display.params.enable_psr != -1)
+               return false;
+       return true;
+}
+
 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp)
 {
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
        return true;
 }
 
+static bool _panel_replay_compute_config(struct intel_dp *intel_dp)
+{
+       struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+       if (!CAN_PANEL_REPLAY(intel_dp))
+               return false;
+
+       if (!panel_replay_global_enabled(intel_dp)) {
+               drm_dbg_kms(&i915->drm, "Panel Replay disabled by flag\n");
+               return false;
+       }
+
+       return true;
+}
+
 void intel_psr_compute_config(struct intel_dp *intel_dp,
                              struct intel_crtc_state *crtc_state,
                              struct drm_connector_state *conn_state)
                return;
        }
 
-       if (CAN_PANEL_REPLAY(intel_dp))
-               crtc_state->has_panel_replay = true;
+       crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp);
 
        crtc_state->has_psr = crtc_state->has_panel_replay ? true :
                _psr_compute_config(intel_dp, crtc_state);