spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC

Add multiple chipselect support for Intel LGM SoCs,
currently QSPI-NOR and QSPI-NAND supported.

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Link: https://lore.kernel.org/r/20201124041840.31066-4-vadivel.muruganx.ramuthevar@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 8c5e83898ae20ec43703a9eb98928f325753ad21..b7ecbc8c1caa1ff00eb18f758f44eb0225174ee3 100644 (file)
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -76,6 +76,7 @@ struct cqspi_st {
        bool                    is_decoded_cs;
        u32                     fifo_depth;
        u32                     fifo_width;
+       u32                     num_chipselect;
        bool                    rclk_en;
        u32                     trigger_address;
        u32                     wr_delay;
@@ -1353,6 +1354,9 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
                return -ENXIO;
        }
 
+       if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
+               cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
+
        cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
 
        return 0;
@@ -1589,6 +1593,8 @@ static int cqspi_probe(struct platform_device *pdev)
        cqspi->current_cs = -1;
        cqspi->sclk = 0;
 
+       master->num_chipselect = cqspi->num_chipselect;
+
        ret = cqspi_setup_flash(cqspi);
        if (ret) {
                dev_err(dev, "failed to setup flash parameters %d\n", ret);