ring_set_paused(engine, 0);
 
+       /*
+        * Sometimes Icelake forgets to reset its pointers on a GPU reset.
+        * Bludgeon them with a mmio update to be sure.
+        */
+       ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
+                    0xffff << 16 | reset_value << 8 | reset_value);
+       ENGINE_POSTING_READ(engine, RING_CONTEXT_STATUS_PTR);
+
        /*
         * After a reset, the HW starts writing into CSB entry [0]. We
         * therefore have to set our HEAD pointer back one entry so that
        WRITE_ONCE(*execlists->csb_write, reset_value);
        wmb(); /* Make sure this is visible to HW (paranoia?) */
 
-       /*
-        * Sometimes Icelake forgets to reset its pointers on a GPU reset.
-        * Bludgeon them with a mmio update to be sure.
-        */
+       invalidate_csb_entries(&execlists->csb_status[0],
+                              &execlists->csb_status[reset_value]);
+
+       /* Once more for luck and our trusty paranoia */
        ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
-                    reset_value << 8 | reset_value);
+                    0xffff << 16 | reset_value << 8 | reset_value);
        ENGINE_POSTING_READ(engine, RING_CONTEXT_STATUS_PTR);
 
-       invalidate_csb_entries(&execlists->csb_status[0],
-                              &execlists->csb_status[reset_value]);
+       GEM_BUG_ON(READ_ONCE(*execlists->csb_write) != reset_value);
 }
 
 static void execlists_sanitize(struct intel_engine_cs *engine)