amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
 }
 
+static int gfx_v11_0_reset_ring(struct amdgpu_ring *ring, unsigned int vmid)
+{
+       int r;
+
+       r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid);
+       if (r)
+               return r;
+
+       /* reset the ring */
+       ring->wptr = 0;
+       *ring->wptr_cpu_addr = 0;
+       amdgpu_ring_clear_ring(ring);
+
+       return amdgpu_ring_test_ring(ring);
+}
+
 static void gfx_v11_ip_print(void *handle, struct drm_printer *p)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
        .soft_recovery = gfx_v11_0_ring_soft_recovery,
        .emit_mem_sync = gfx_v11_0_emit_mem_sync,
+       .reset = gfx_v11_0_reset_ring,
 };
 
 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
        .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
        .soft_recovery = gfx_v11_0_ring_soft_recovery,
        .emit_mem_sync = gfx_v11_0_emit_mem_sync,
+       .reset = gfx_v11_0_reset_ring,
 };
 
 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {