drm/i915: pass dev_priv explicitly to TRANS_VTOTAL

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_VTOTAL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/751bc7046f5e2c5fc6a4fe5ade2e836c641abdb7.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index f87a2170ac917e81d23c19e42f9f588df30e4f65..f95709321ea61fec509f12e33d23a79720fbc9cb 100644 (file)
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -953,7 +953,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
                 * struct drm_display_mode.
                 * For interlace mode: program required pixel minus 2
                 */
-               intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans),
+               intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, dsi_trans),
                               VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
        }
 

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 10e95dc425a696f50c0deb6895644112c6522bb7..29ab5b112b86e4d56129a65099d27f1d0b49a708 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -708,7 +708,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
        drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
 
        save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));
-       save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
+       save_vtotal = intel_de_read(dev_priv,
+                                   TRANS_VTOTAL(dev_priv, cpu_transcoder));
        vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
 
        vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 111f2c400ecd3f9686325ceef19ccdc0b68394eb..c681a23be1eb151aae900c8602c0769910a7e10b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2720,7 +2720,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
                       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
                       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
 
-       intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
+       intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
                       VACTIVE(crtc_vdisplay - 1) |
                       VTOTAL(crtc_vtotal - 1));
        intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
@@ -2736,7 +2736,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
         * bits. */
        if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
            (pipe == PIPE_B || pipe == PIPE_C))
-               intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
+               intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, pipe),
                               VACTIVE(crtc_vdisplay - 1) |
                               VTOTAL(crtc_vtotal - 1));
 }
@@ -2767,7 +2767,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
         * The double buffer latch point for TRANS_VTOTAL
         * is the transcoder's undelayed vblank.
         */
-       intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
+       intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
                       VACTIVE(crtc_vdisplay - 1) |
                       VTOTAL(crtc_vtotal - 1));
 }
@@ -2826,7 +2826,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
        adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
        adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
 
-       tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
+       tmp = intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder));
        adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
        adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
 
@@ -8196,7 +8196,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
                       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
        intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
                       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
-       intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
+       intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
                       VACTIVE(480 - 1) | VTOTAL(525 - 1));
        intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
                       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));

diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 480c0e09434d5c87b2a090ebe058a7e1ad680a2e..611a9cd2596f4529550f93bafe2abac9bed3745a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -231,7 +231,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
                       intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder)));
 
        intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
-                      intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));
+                      intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)));
        intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
                       intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)));
        intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 0d972ef4871c0ab324326afe5b6d63872f8a19e6..45b1dbd5881a813ae59afb8c677a927b923818dd 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -677,7 +677,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
 
        /* Get H/V total from transcoder timing */
        htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
-       vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
+       vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
 
        if (dp_br && link_n && htotal && vtotal) {
                u64 pixel_clk = 0;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index faee5ad2d5bec9eb98c557964195ccf2003239df..fe61cd0dae6ec353e3affc47e7a94fbbd6fb6a80 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1139,7 +1139,7 @@
 #define TRANS_HTOTAL(dev_priv, trans)  _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
 #define TRANS_HBLANK(dev_priv, trans)  _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
 #define TRANS_HSYNC(dev_priv, trans)   _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
-#define TRANS_VTOTAL(trans)    _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
+#define TRANS_VTOTAL(dev_priv, trans)  _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
 #define TRANS_VBLANK(trans)    _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
 #define TRANS_VSYNC(trans)     _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
 #define BCLRPAT(trans)         _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 09d8960f7398001814a22d568f5ec16f8c008267..5dd85943e0a13841fac6d7ce3423b23f89795b7b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -234,7 +234,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
        MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
        MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));
-       MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
+       MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));
        MMIO_D(TRANS_VBLANK(TRANSCODER_A));
        MMIO_D(TRANS_VSYNC(TRANSCODER_A));
        MMIO_D(BCLRPAT(TRANSCODER_A));
@@ -243,7 +243,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
-       MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
+       MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_VBLANK(TRANSCODER_B));
        MMIO_D(TRANS_VSYNC(TRANSCODER_B));
        MMIO_D(BCLRPAT(TRANSCODER_B));
@@ -252,7 +252,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
-       MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
+       MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_VBLANK(TRANSCODER_C));
        MMIO_D(TRANS_VSYNC(TRANSCODER_C));
        MMIO_D(BCLRPAT(TRANSCODER_C));
@@ -261,7 +261,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
        MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
        MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
-       MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
+       MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));
        MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
        MMIO_D(TRANS_VSYNC(TRANSCODER_EDP));
        MMIO_D(BCLRPAT(TRANSCODER_EDP));