Merge tag 'drm-next-2024-07-18' of https://gitlab.freedesktop.org/drm/kernel

Pull drm updates from Dave Airlie:
 "There's a lot of stuff in here, amd, i915 and xe have new platform
  work, lots of core rework around EDID handling, some new COMPILE_TEST
  options, maintainer changes and a lots of other stuff. Summary:

  core:
   - deprecate DRM data and return 0 date
   - connector: Create a set of helpers to help with HDMI support
   - Remove driver owner assignments
   - Allow more drivers to compile with COMPILE_TEST
   - Conversions to drm_edid
   - Sprinkle MODULE_DESCRIPTIONS everywhere they are missing
   - Remove drm_mm_replace_node
   - print: Add a drm prefix to warn level messages too, remove
            ___drm_dbg, consolidate prefix handling
   - New monochrome TV mode variant

  ttm:
   - improve number of page faults on some platforms
   - fix test builds under PREEMPT_RT
   - more test coverage

  ci:
   - Require a more recent version of mesa
   - improve farm setup and test generation

  dma-buf:
   - warn if reserving 0 fence slots
   - internal API heap enhancements

  fbdev:
   - Create memory manager optimized fbdev emulation

  panic:
   - Allow to select fonts
   - improve drm_fb_dma_get_scanout_buffer
   - Allow to dump kmsg to the screen

  bridge:
   - Remove redundant checks on bridge->encoder
   - Remove drm_bridge_chain_mode_fixup
   - bridge-connector: Plumb in the new HDMI helper
   - analogix_dp: Various improvements, handle AUX transfers timeout
   - samsung-dsim: Fix timings calculation
   - tc358767: Plenty of small fixes, fix no connector attach, fix
               clocks
   - sii902x: state validation improvements

  panels:
   - Switch panels from register table initialization to proper code
   - Now that the panel code tracks the panel state, remove every ad-hoc
     implementation in the panel drivers
   - More cleanup of prepare / enable state tracking in drivers
   - edp: Drop legacy panel compatibles
   - simple-bridge: Switch to devm_drm_bridge_add
   - New panels: Lincoln Tech Sol LCD185-101CT, Microtips Technology
                 13-101HIEBCAF0-C, Microtips Technology MF-103HIEB0GA0,
                 BOE nv110wum-l60, IVO t109nw41, WL-355608-A8, PrimeView
                 PM070WL4, Lincoln Technologies LCD197, Ortustech
                 COM35H3P70ULC, AUO G104STN01, K&d kd101ne3-40ti

  amdgpu:
   - DCN 4.0.x support
   - GC 12.0 support
   - GMC 12.0 support
   - SDMA 7.0 support
   - MES12 support
   - MMHUB 4.1 support
   - GFX12 modifier and DCC support
   - lots of IP fixes/updates

  amdkfd:
   - Contiguous VRAM allocations
   - GC 12.0 support
   - SDMA 7.0 support
   - SR-IOV fixes
   - KFD GFX ALU exceptions

  i915:
   - Battlemage Xe2 HPD display enablement
   - Panel Replay enabling
   - DP AUX-less ALPM/LOBF
   - Enable link training failure fallback for DP MST links
   - CMRR (Content Match Refresh Rate) enabling
   - Increase ADL-S/ADL-P/DG2+ max TMDS bitrate to 6 Gbps
   - Enable eDP AUX based HDR backlight
   - Support replaying GPU hangs with captured context image
   - Automate CCS Mode setting during engine resets
   - lots of refactoring
   - Support replaying GPU hangs with captured context image
   - Increase FLR timeout from 3s to 9s
   - Enable w/a 16021333562 for DG2, MTL and ARL [guc]

  xe:
   - update MAINATINERS
   - New uapi adding OA functionality to Xe
   - expose l3 bank mask
   - fix display detect on ADL-N
   - runtime PM Fixes
   - Fix silent backmerge issues
   - More prep for SR-IOV
   - HWmon additions
   - per client usage info
   - Rework GPU page fault handling
   - Drop EXEC_QUEUE_FLAG_BANNED
   - Add BMG PCI IDs
   - Scheduler fixes and improvements
   - Rename xe_exec_queue::compute to xe_exec_queue::lr
   - Use ttm_uncached for BO with NEEDS_UC flag
   - Rename xe perf layer as xe observation layer
   - lots of refactoring

  radeon:
   - Backlight workaround for iMac
   - Silence UBSAN flex array warnings

  msm:
   - Validate registers XML description against schema in CI
   - core/dpu: SM7150 support
   - mdp5: Add support for MSM8937
   - gpu: Add param for userspace to know if raytracing is supported
   - gpu: X185 support (aka gpu in X1 laptop chips)
   - gpu: a505 support

  ivpu:
   - hardware scheduler support
   - profiling support
   - improvements to the platform support layer
   - firmware handling improvements
   - clocks/power mgmt improvements
   - scheduler/logging improvements

  habanalabs:
   - Gradual sleep in polling memory macro
   - Reduce Gaudi2 MSI-X interrupt count to 128
   - Add Gaudi2-D revision support
   - Add timestamp to CPLD info
   - Gaudi2: Assume hard-reset by firmware upon MC SEI severe error
   - Align Gaudi2 interrupt names
   - Check for errors after preboot is ready
   - Change habanalabs maintainer and git repo path

  mgag200:
   - refactoring and improvements
   - Add BMC output
   - enable polling

  nouveau:
   - add registry command line

  v3d:
   - perf counters improvements

  zynqmp:
   - irq and debugfs improvements

  atmel-hlcdc:
   - Support XLCDC in sam9x7

  mipi-dbi:
   - Remove mipi_dbi_machine_little_endian
   - make SPI bits per word configurable
   - support RGB888
   - allow pixel formats to be specified in the DT

  sun4i:
   - Rework the blender setup for DE2

  panfrost:
   - Enable MT8188 support

  vc4:
   - Monochrome TV support

  exynos:
   - fix fallback mode regression
   - fix memory leak
   - Use drm_edid_duplicate() instead of kmemdup()

  etnaviv:
   - fix i.MX8MP NPU clock gating
   - workaround FE register cdc issues on some cores
   - fix DMA sync handling for cached buffers
   - fix job timeout handling
   - keep TS enabled on MMUv2 cores for improved performance

  mediatek:
   - Convert to platform remove callback returning void-
   - Drop chain_mode_fixup call in mode_valid()
   - Fixes the errors of MediaTek display driver found by IGT
   - Add display support for the MT8365-EVK board
   - Fix bit depth overwritten for mtk_ovl_set bit_depth()
   - Fix possible_crtcs calculation
   - Fix spurious kfree()

  ast:
   - refactor mode setting code

  stm:
   - Add LVDS support
   - DSI PHY updates"

* tag 'drm-next-2024-07-18' of https://gitlab.freedesktop.org/drm/kernel: (2501 commits)
  drm/amdgpu/mes12: add missing opcode string
  drm/amdgpu/mes11: update opcode strings
  Revert "drm/amd/display: Reset freesync config before update new state"
  drm/omap: Restrict compile testing to PAGE_SIZE less than 64KB
  drm/xe: Drop trace_xe_hw_fence_free
  drm/xe/uapi: Rename xe perf layer as xe observation layer
  drm/amdgpu: remove exp hw support check for gfx12
  drm/amdgpu: timely save bad pages to eeprom after gpu ras reset is completed
  drm/amdgpu: flush all cached ras bad pages to eeprom
  drm/amdgpu: select compute ME engines dynamically
  drm/amd/display: Allow display DCC for DCN401
  drm/amdgpu: select compute ME engines dynamically
  drm/amdgpu/job: Replace DRM_INFO/ERROR logging
  drm/amdgpu: select compute ME engines dynamically
  drm/amd/pm: Ignore initial value in smu response register
  drm/amdgpu: Initialize VF partition mode
  drm/amd/amdgpu: fix SDMA IRQ client ID <-> req mapping
  MAINTAINERS: fix Xinhui's name
  MAINTAINERS: update powerplay and swsmu
  drm/qxl: Pin buffer objects for internal mappings
  ...

diff --cc Documentation/devicetree/bindings/vendor-prefixes.yaml
Simple merge

diff --cc MAINTAINERS
Simple merge

diff --cc drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
Simple merge

diff --cc drivers/gpu/drm/drm_fbdev_ttm.c
Simple merge

diff --cc drivers/gpu/drm/drm_panel_orientation_quirks.c
Simple merge

diff --cc drivers/gpu/drm/nouveau/nouveau_connector.c
Simple merge

diff --cc drivers/gpu/drm/panthor/panthor_sched.c
index 9a0ff48f7061d7115b037395fc4f4b8caf12de74,42929e1471077fd9cd7d6d3b76b799f7dbf6d3a1..463bcd3cf00f35b87d0d9a17c798f05f66a54e50
--- 1/drivers/gpu/drm/panthor/panthor_sched.c
--- 2/drivers/gpu/drm/panthor/panthor_sched.c
+++ b/drivers/gpu/drm/panthor/panthor_sched.c
@@@ -2939,12 -2926,9 +2939,13 @@@ queue_run_job(struct drm_sched_job *sch
                        pm_runtime_get(ptdev->base.dev);
                        sched->pm.has_ref = true;
                }
+               panthor_devfreq_record_busy(sched->ptdev);
        }
  
 +      /* Update the last fence. */
 +      dma_fence_put(queue->fence_ctx.last_fence);
 +      queue->fence_ctx.last_fence = dma_fence_get(job->done_fence);
 +
        done_fence = dma_fence_get(job->done_fence);
  
  out_unlock:

diff --cc drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
Simple merge

diff --cc drivers/gpu/drm/xe/xe_bo.c
index b6f3a43d637f704e8cbd4e7f6e66202607037ec8,65c696966e96c476cb2e25c5132a11fabad2f2c9..31192d983d9e195531def2437d37a049795deea7
--- 1/drivers/gpu/drm/xe/xe_bo.c
--- 2/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@@ -331,36 -357,36 +357,45 @@@ static struct ttm_tt *xe_ttm_tt_create(
                extra_pages = DIV_ROUND_UP(xe_device_ccs_bytes(xe, bo->size),
                                           PAGE_SIZE);
  
 -      switch (bo->cpu_caching) {
 -      case DRM_XE_GEM_CPU_CACHING_WC:
 -              caching = ttm_write_combined;
 -              break;
 -      default:
 -              caching = ttm_cached;
 -              break;
 -      }
 -
 -      WARN_ON((bo->flags & XE_BO_FLAG_USER) && !bo->cpu_caching);
 -
        /*
 -       * Display scanout is always non-coherent with the CPU cache.
 -       *
 -       * For Xe_LPG and beyond, PPGTT PTE lookups are also non-coherent and
 -       * require a CPU:WC mapping.
 +       * DGFX system memory is always WB / ttm_cached, since
 +       * other caching modes are only supported on x86. DGFX
 +       * GPU system memory accesses are always coherent with the
 +       * CPU.
         */
 -      if ((!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) ||
 -          (xe->info.graphics_verx100 >= 1270 && bo->flags & XE_BO_FLAG_PAGETABLE))
 -              caching = ttm_write_combined;
 +      if (!IS_DGFX(xe)) {
 +              switch (bo->cpu_caching) {
 +              case DRM_XE_GEM_CPU_CACHING_WC:
 +                      caching = ttm_write_combined;
 +                      break;
 +              default:
 +                      caching = ttm_cached;
 +                      break;
 +              }
 +
 +              WARN_ON((bo->flags & XE_BO_FLAG_USER) && !bo->cpu_caching);
 +
 +              /*
 +               * Display scanout is always non-coherent with the CPU cache.
 +               *
 +               * For Xe_LPG and beyond, PPGTT PTE lookups are also
 +               * non-coherent and require a CPU:WC mapping.
 +               */
 +              if ((!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) ||
 +                  (xe->info.graphics_verx100 >= 1270 &&
 +                   bo->flags & XE_BO_FLAG_PAGETABLE))
 +                      caching = ttm_write_combined;
 +      }
  
+       if (bo->flags & XE_BO_FLAG_NEEDS_UC) {
+               /*
+                * Valid only for internally-created buffers only, for
+                * which cpu_caching is never initialized.
+                */
+               xe_assert(xe, bo->cpu_caching == 0);
+               caching = ttm_uncached;
+       }
+ 
        err = ttm_tt_init(&tt->ttm, &bo->ttm, page_flags, caching, extra_pages);
        if (err) {
                kfree(tt);

diff --cc drivers/platform/x86/intel_ips.c
index c62c3c4ec20a29feed70bc303ca6d624734e0010,523fb18a7ace069d0ee650e1c05e638d3feee65c..79a7b68c737303ea59c7588f5a44cfa98df3aa81
--- 1/drivers/platform/x86/intel_ips.c
--- 2/drivers/platform/x86/intel_ips.c
+++ b/drivers/platform/x86/intel_ips.c
@@@ -59,10 -59,9 +59,10 @@@
  #include <linux/tick.h>
  #include <linux/timer.h>
  #include <linux/dmi.h>
- #include <drm/i915_drm.h>
+ #include <drm/intel/i915_drm.h>
  #include <asm/msr.h>
  #include <asm/processor.h>
 +#include <asm/cpu_device_id.h>
  #include "intel_ips.h"
  
  #include <linux/io-64-nonatomic-lo-hi.h>

diff --cc include/uapi/drm/xe_drm.h
Simple merge