tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
 
        PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-                               CG_TACH_STATUS, TACH_PERIOD, tach_period);
+                               CG_TACH_CTRL, TARGET_PERIOD, tach_period);
 
        return smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
 }
 
        if (!result) {
                crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
                tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
-               WREG32_SOC15(THM, 0, mmCG_TACH_STATUS,
-                               REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
-                                       CG_TACH_STATUS, TACH_PERIOD,
+               WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
+                               REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
+                                       CG_TACH_CTRL, TARGET_PERIOD,
                                        tach_period));
        }
        return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);