KVM: arm64: Add save/restore for PIR{,E0}_EL2

Like their EL1 equivalent, the EL2-specific FEAT_S1PIE registers
are context-switched. This is made conditional on both FEAT_TCRX
and FEAT_S1PIE being adversised.

Note that this change only makes sense if read together with the
issue D22677 contained in 102105_K.a_04_en.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241023145345.1613824-16-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c
index cdbf52bfc4833092437b110aa9daf16a80f3cfb6..a603966726f653fa7f74d60a6fba7af2cb9594d5 100644 (file)
--- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c
+++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c
@@ -51,9 +51,15 @@ static void __sysreg_save_vel2_state(struct kvm_vcpu *vcpu)
                __vcpu_sys_reg(vcpu, TTBR1_EL2) = read_sysreg_el1(SYS_TTBR1);
                __vcpu_sys_reg(vcpu, TCR_EL2)   = read_sysreg_el1(SYS_TCR);
 
-               if (ctxt_has_tcrx(&vcpu->arch.ctxt))
+               if (ctxt_has_tcrx(&vcpu->arch.ctxt)) {
                        __vcpu_sys_reg(vcpu, TCR2_EL2) = read_sysreg_el1(SYS_TCR2);
 
+                       if (ctxt_has_s1pie(&vcpu->arch.ctxt)) {
+                               __vcpu_sys_reg(vcpu, PIRE0_EL2) = read_sysreg_el1(SYS_PIRE0);
+                               __vcpu_sys_reg(vcpu, PIR_EL2) = read_sysreg_el1(SYS_PIR);
+                       }
+               }
+
                /*
                 * The EL1 view of CNTKCTL_EL1 has a bunch of RES0 bits where
                 * the interesting CNTHCTL_EL2 bits live. So preserve these
@@ -110,9 +116,14 @@ static void __sysreg_restore_vel2_state(struct kvm_vcpu *vcpu)
                write_sysreg_el1(val, SYS_TCR);
        }
 
-       if (ctxt_has_tcrx(&vcpu->arch.ctxt))
+       if (ctxt_has_tcrx(&vcpu->arch.ctxt)) {
                write_sysreg_el1(__vcpu_sys_reg(vcpu, TCR2_EL2), SYS_TCR2);
 
+               if (ctxt_has_s1pie(&vcpu->arch.ctxt)) {
+                       write_sysreg_el1(__vcpu_sys_reg(vcpu, PIR_EL2), SYS_PIR);
+                       write_sysreg_el1(__vcpu_sys_reg(vcpu, PIRE0_EL2), SYS_PIRE0);
+               }
+       }
 
        write_sysreg_el1(__vcpu_sys_reg(vcpu, ESR_EL2),         SYS_ESR);
        write_sysreg_el1(__vcpu_sys_reg(vcpu, AFSR0_EL2),       SYS_AFSR0);