ice: Change CGU regs struct to anonymous

Simplify the code by using anonymous struct in CGU registers instead of
naming each structure 'field'.

Suggested-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Link: https://lore.kernel.org/r/20240528-next-2024-05-28-ptp-refactors-v1-8-c082739bb6f6@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/intel/ice/ice_cgu_regs.h b/drivers/net/ethernet/intel/ice/ice_cgu_regs.h
index 57abd52386d0d202431ec0dc55dd63a7e5aa9f93..36aeb10eefb7303977bbcbdd5250a46b5231edab 100644 (file)
--- a/drivers/net/ethernet/intel/ice/ice_cgu_regs.h
+++ b/drivers/net/ethernet/intel/ice/ice_cgu_regs.h
@@ -23,7 +23,7 @@ union nac_cgu_dword9 {
                u32 clk_synce0_amp : 2;
                u32 one_pps_out_amp : 2;
                u32 misc24 : 12;
-       } field;
+       };
        u32 val;
 };
 
@@ -39,7 +39,7 @@ union nac_cgu_dword19 {
                u32 japll_ndivratio : 4;
                u32 japll_iref_ndivratio : 3;
                u32 misc27 : 1;
-       } field;
+       };
        u32 val;
 };
 
@@ -63,7 +63,7 @@ union nac_cgu_dword22 {
                u32 fdpllclk_sel_div2 : 1;
                u32 time1588clk_sel_div2 : 1;
                u32 misc3 : 1;
-       } field;
+       };
        u32 val;
 };
 
@@ -77,7 +77,7 @@ union nac_cgu_dword24 {
                u32 ext_synce_sel : 1;
                u32 ref1588_ck_div : 4;
                u32 time_ref_sel : 1;
-       } field;
+       };
        u32 val;
 };
 
@@ -92,7 +92,7 @@ union tspll_cntr_bist_settings {
                u32 i_plllock_cnt_6_0 : 7;
                u32 i_plllock_cnt_10_7 : 4;
                u32 reserved200 : 4;
-       } field;
+       };
        u32 val;
 };
 
@@ -109,7 +109,7 @@ union tspll_ro_bwm_lf {
                u32 afcdone_cri : 1;
                u32 feedfwrdgain_cal_cri_7_0 : 8;
                u32 m2fbdivmod_cri_7_0 : 8;
-       } field;
+       };
        u32 val;
 };
 

diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index 1b333b1c2738a236e2336b0f2fabe3d7a041c96e..691ea20811e726e614846ee25734ab03e7f4501e 100644 (file)
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -393,14 +393,14 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
 
        /* Log the current clock configuration */
        ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
-                 dw24.field.ts_pll_enable ? "enabled" : "disabled",
-                 ice_clk_src_str(dw24.field.time_ref_sel),
-                 ice_clk_freq_str(dw9.field.time_ref_freq_sel),
-                 bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked");
+                 dw24.ts_pll_enable ? "enabled" : "disabled",
+                 ice_clk_src_str(dw24.time_ref_sel),
+                 ice_clk_freq_str(dw9.time_ref_freq_sel),
+                 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
 
        /* Disable the PLL before changing the clock source or frequency */
-       if (dw24.field.ts_pll_enable) {
-               dw24.field.ts_pll_enable = 0;
+       if (dw24.ts_pll_enable) {
+               dw24.ts_pll_enable = 0;
 
                err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
                if (err)
@@ -408,7 +408,7 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
        }
 
        /* Set the frequency */
-       dw9.field.time_ref_freq_sel = clk_freq;
+       dw9.time_ref_freq_sel = clk_freq;
        err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
        if (err)
                return err;
@@ -418,8 +418,8 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
        if (err)
                return err;
 
-       dw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
-       dw19.field.tspll_ndivratio = 1;
+       dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
+       dw19.tspll_ndivratio = 1;
 
        err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
        if (err)
@@ -430,8 +430,8 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
        if (err)
                return err;
 
-       dw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
-       dw22.field.time1588clk_sel_div2 = 0;
+       dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
+       dw22.time1588clk_sel_div2 = 0;
 
        err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
        if (err)
@@ -442,16 +442,16 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
        if (err)
                return err;
 
-       dw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
-       dw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
-       dw24.field.time_ref_sel = clk_src;
+       dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
+       dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
+       dw24.time_ref_sel = clk_src;
 
        err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
        if (err)
                return err;
 
        /* Finally, enable the PLL */
-       dw24.field.ts_pll_enable = 1;
+       dw24.ts_pll_enable = 1;
 
        err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
        if (err)
@@ -464,17 +464,17 @@ static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
        if (err)
                return err;
 
-       if (!bwm_lf.field.plllock_true_lock_cri) {
+       if (!bwm_lf.plllock_true_lock_cri) {
                dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
                return -EBUSY;
        }
 
        /* Log the current clock configuration */
        ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
-                 dw24.field.ts_pll_enable ? "enabled" : "disabled",
-                 ice_clk_src_str(dw24.field.time_ref_sel),
-                 ice_clk_freq_str(dw9.field.time_ref_freq_sel),
-                 bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked");
+                 dw24.ts_pll_enable ? "enabled" : "disabled",
+                 ice_clk_src_str(dw24.time_ref_sel),
+                 ice_clk_freq_str(dw9.time_ref_freq_sel),
+                 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
 
        return 0;
 }
@@ -499,8 +499,8 @@ static int ice_init_cgu_e82x(struct ice_hw *hw)
                return err;
 
        /* Disable sticky lock detection so lock err reported is accurate */
-       cntr_bist.field.i_plllock_sel_0 = 0;
-       cntr_bist.field.i_plllock_sel_1 = 0;
+       cntr_bist.i_plllock_sel_0 = 0;
+       cntr_bist.i_plllock_sel_1 = 0;
 
        err = ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
                                     cntr_bist.val);