ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x

McASP1 TX interrupt is 30, not 32 on DM646x DMSoC.

While at it remove the bogus AEMIF interrupt entry from
dm646x_default_priorities[]. AEMIF interrupt on DM6467 is
60 not 30 and the entry for the correct interrupt number
is already present in the same table.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[nsekhar@ti.com: remove bogus entry from dm646x_default_priorities[]]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index d2a2619aee81d7d844b3473f0c8289f94e0cc27f..58769eddd3c35f9a4e47689530b74052952863c0 100644 (file)
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -493,7 +493,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
        [IRQ_DM646X_EMACMISCINT]        = 7,
        [IRQ_DM646X_MCASP0TXINT]        = 7,
        [IRQ_DM646X_MCASP0RXINT]        = 7,
-       [IRQ_AEMIFINT]                  = 7,
        [IRQ_DM646X_RESERVED_3]         = 7,
        [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
        [IRQ_TINT0_TINT34]              = 7,    /* clocksource */

diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 354af71798dcd4e09206ae6e82bfa862b4ccb0a1..edb2ca62321ae141ed6e5a9afe910e88b423bbe9 100644 (file)
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -129,8 +129,8 @@
 #define IRQ_DM646X_EMACMISCINT  27
 #define IRQ_DM646X_MCASP0TXINT  28
 #define IRQ_DM646X_MCASP0RXINT  29
+#define IRQ_DM646X_MCASP1TXINT  30
 #define IRQ_DM646X_RESERVED_3   31
-#define IRQ_DM646X_MCASP1TXINT  32
 #define IRQ_DM646X_VLQINT       38
 #define IRQ_DM646X_UARTINT2     42
 #define IRQ_DM646X_SPINT0       43