drm/msm/disp/dpu1: add support to program fetch active in ctl path

A new register called CTL_FETCH_ACTIVE is introduced in
SC7280 family which is used to inform the HW about
the pipes which are active in the current ctl path.
This change adds support to program this register
based on the active pipes in the current composition.

Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Link: https://lore.kernel.org/r/1617685792-14376-4-git-send-email-mkrishn@codeaurora.org
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 2a70f029e6ed80858c095d33cf900e31f60c152c..8602b8507ec5054e32f9a8de17379fa3c34a40e0 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -209,7 +209,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
        uint32_t stage_idx, lm_idx;
        int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 };
        bool bg_alpha_enable = false;
+       DECLARE_BITMAP(fetch_active, SSPP_MAX);
 
+       memset(fetch_active, 0, sizeof(fetch_active));
        drm_atomic_crtc_for_each_plane(plane, crtc) {
                state = plane->state;
                if (!state)
@@ -219,7 +221,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
                fb = state->fb;
 
                dpu_plane_get_ctl_flush(plane, ctl, &flush_mask);
-
+               set_bit(dpu_plane_pipe(plane), fetch_active);
                DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
                                crtc->base.id,
                                pstate->stage,
@@ -259,6 +261,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
                }
        }
 
+       if (ctl->ops.set_active_pipes)
+               ctl->ops.set_active_pipes(ctl, fetch_active);
+
         _dpu_crtc_program_lm_output_roi(crtc);
 }
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 92e6f1b94738682c54e6b1fe6f085a6868846f01..2d4645e01ebf6ef70b8443b3ae79fc79c4f93b6b 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -27,6 +27,7 @@
 #define   CTL_MERGE_3D_FLUSH            0x100
 #define   CTL_INTF_FLUSH                0x110
 #define   CTL_INTF_MASTER               0x134
+#define   CTL_FETCH_PIPE_ACTIVE         0x0FC
 
 #define CTL_MIXER_BORDER_OUT            BIT(24)
 #define CTL_FLUSH_MASK_CTL              BIT(17)
@@ -34,6 +35,11 @@
 #define DPU_REG_RESET_TIMEOUT_US        2000
 #define  MERGE_3D_IDX   23
 #define  INTF_IDX       31
+#define CTL_INVALID_BIT                 0xffff
+
+static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,
+       CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0,
+       1, 2, 3, CTL_INVALID_BIT, CTL_INVALID_BIT};
 
 static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
                const struct dpu_mdss_cfg *m,
@@ -344,6 +350,8 @@ static void dpu_hw_ctl_clear_all_blendstages(struct dpu_hw_ctl *ctx)
                DPU_REG_WRITE(c, CTL_LAYER_EXT2(LM_0 + i), 0);
                DPU_REG_WRITE(c, CTL_LAYER_EXT3(LM_0 + i), 0);
        }
+
+       DPU_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0);
 }
 
 static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
@@ -531,6 +539,23 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
        DPU_REG_WRITE(c, CTL_TOP, intf_cfg);
 }
 
+static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx,
+       unsigned long *fetch_active)
+{
+       int i;
+       u32 val = 0;
+
+       if (fetch_active) {
+               for (i = 0; i < SSPP_MAX; i++) {
+                       if (test_bit(i, fetch_active) &&
+                               fetch_tbl[i] != CTL_INVALID_BIT)
+                               val |= BIT(fetch_tbl[i]);
+               }
+       }
+
+       DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val);
+}
+
 static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
                unsigned long cap)
 {
@@ -560,6 +585,8 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
        ops->get_bitmask_sspp = dpu_hw_ctl_get_bitmask_sspp;
        ops->get_bitmask_mixer = dpu_hw_ctl_get_bitmask_mixer;
        ops->get_bitmask_dspp = dpu_hw_ctl_get_bitmask_dspp;
+       if (cap & BIT(DPU_CTL_FETCH_ACTIVE))
+               ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active;
 };
 
 static struct dpu_hw_blk_ops dpu_hw_ops;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index e93a42ab60b1e8de74de2994e0896d59ec751ce0..806c171e5df210a26ef4a906e56a12fcc4789d1d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -167,6 +167,9 @@ struct dpu_hw_ctl_ops {
         */
        void (*setup_blendstage)(struct dpu_hw_ctl *ctx,
                enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);
+
+       void (*set_active_pipes)(struct dpu_hw_ctl *ctx,
+               unsigned long *fetch_active);
 };
 
 /**