riscv: traps_misaligned: properly sign extend value in misaligned load handler

Add missing cast to signed long.

Signed-off-by: Andreas Schwab <schwab@suse.de>
Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE")
Tested-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/mvmikk0goil.fsf@suse.de
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>

diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 93043924fe6c608c9fa8ee322096450a3963e614..f760e4fcc052d24b5398e4cf9fb77e02e4d65af1 100644 (file)
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)
        }
 
        if (!fp)
-               SET_RD(insn, regs, val.data_ulong << shift >> shift);
+               SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift);
        else if (len == 8)
                set_f64_rd(insn, regs, val.data_u64);
        else