ch->enabled_tc = !i40e_is_channel_macvlan(ch) && enabled_tc;
        ch->seid = ctxt.seid;
        ch->vsi_number = ctxt.vsi_number;
-       ch->stat_counter_idx = cpu_to_le16(ctxt.info.stat_counter_idx);
+       ch->stat_counter_idx = le16_to_cpu(ctxt.info.stat_counter_idx);
 
        /* copy just the sections touched not the entire info
         * since not all sections are valid as returned by
 i40e_set_cld_element(struct i40e_cloud_filter *filter,
                     struct i40e_aqc_cloud_filters_element_data *cld)
 {
-       int i, j;
        u32 ipa;
+       int i;
 
        memset(cld, 0, sizeof(*cld));
        ether_addr_copy(cld->outer_mac, filter->dst_mac);
 
        if (filter->n_proto == ETH_P_IPV6) {
 #define IPV6_MAX_INDEX (ARRAY_SIZE(filter->dst_ipv6) - 1)
-               for (i = 0, j = 0; i < ARRAY_SIZE(filter->dst_ipv6);
-                    i++, j += 2) {
+               for (i = 0; i < ARRAY_SIZE(filter->dst_ipv6); i++) {
                        ipa = be32_to_cpu(filter->dst_ipv6[IPV6_MAX_INDEX - i]);
-                       ipa = cpu_to_le32(ipa);
-                       memcpy(&cld->ipaddr.raw_v6.data[j], &ipa, sizeof(ipa));
+
+                       *(__le32 *)&cld->ipaddr.raw_v6.data[i * 2] = cpu_to_le32(ipa);
                }
        } else {
                ipa = be32_to_cpu(filter->dst_ipv4);
+
                memcpy(&cld->ipaddr.v4.data, &ipa, sizeof(ipa));
        }
 
 
        skb_record_rx_queue(skb, rx_ring->queue_index);
 
        if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
-               u16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1;
+               __le16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1;
 
                __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
                                       le16_to_cpu(vlan_tag));
 
        struct i40e_tx_desc *tx_desc;
 
        tx_desc = I40E_TX_DESC(xdp_ring, ntu);
-       tx_desc->cmd_type_offset_bsz |= (I40E_TX_DESC_CMD_RS << I40E_TXD_QW1_CMD_SHIFT);
+       tx_desc->cmd_type_offset_bsz |= cpu_to_le64(I40E_TX_DESC_CMD_RS << I40E_TXD_QW1_CMD_SHIFT);
 }
 
 /**