drm/i915/display: Add DDR5 and LPDDR5 BW buddy page entries

Set the right BW buddy page mask for new memory types.

BSpec: 49218
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210209174238.153278-1-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e17b1ca356c3cd8d07080f2ab27f4000602878f2..f00c1750febd348e673bf8d7e8cada847d74c4c6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5317,17 +5317,25 @@ struct buddy_page_mask {
 
 static const struct buddy_page_mask tgl_buddy_page_masks[] = {
        { .num_channels = 1, .type = INTEL_DRAM_DDR4,   .page_mask = 0xF },
+       { .num_channels = 1, .type = INTEL_DRAM_DDR5,   .page_mask = 0xF },
        { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C },
+       { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1C },
        { .num_channels = 2, .type = INTEL_DRAM_DDR4,   .page_mask = 0x1F },
+       { .num_channels = 2, .type = INTEL_DRAM_DDR5,   .page_mask = 0x1E },
        { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 },
+       { .num_channels = 4, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x38 },
        {}
 };
 
 static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = {
        { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 },
        { .num_channels = 1, .type = INTEL_DRAM_DDR4,   .page_mask = 0x1 },
+       { .num_channels = 1, .type = INTEL_DRAM_DDR5,   .page_mask = 0x1 },
+       { .num_channels = 1, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1 },
        { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 },
        { .num_channels = 2, .type = INTEL_DRAM_DDR4,   .page_mask = 0x3 },
+       { .num_channels = 2, .type = INTEL_DRAM_DDR5,   .page_mask = 0x3 },
+       { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x3 },
        {}
 };