arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition names

Normally we include the full register name in the defines for fields within
registers but this has not been followed for ID registers. In preparation
for automatic generation of defines add the _EL1s into the defines for
ID_AA64ISAR2_EL1 to follow the convention. No functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220704170302.2609529-17-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/asm_pointer_auth.h b/arch/arm64/include/asm/asm_pointer_auth.h
index 3b192e04a5dd2b4ba6380b005b3c9ed6ea41eeba..13ecc79854ee2312dd25989072a5f78843c6bf20 100644 (file)
--- a/arch/arm64/include/asm/asm_pointer_auth.h
+++ b/arch/arm64/include/asm/asm_pointer_auth.h
@@ -61,7 +61,7 @@ alternative_else_nop_endif
        mrs     \tmp1, id_aa64isar1_el1
        ubfx    \tmp1, \tmp1, #ID_AA64ISAR1_EL1_APA_SHIFT, #8
        mrs_s   \tmp2, SYS_ID_AA64ISAR2_EL1
-       ubfx    \tmp2, \tmp2, #ID_AA64ISAR2_APA3_SHIFT, #4
+       ubfx    \tmp2, \tmp2, #ID_AA64ISAR2_EL1_APA3_SHIFT, #4
        orr     \tmp1, \tmp1, \tmp2
        cbz     \tmp1, .Lno_addr_auth\@
        mov_q   \tmp1, (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | \

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 6472f2badc973640d5c5ad2e1535d64062ebd2c3..fe59035bdc220d64e28f3dfc5799a3daaaab8ec4 100644 (file)
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -673,7 +673,7 @@ static inline bool supports_clearbhb(int scope)
                isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);
 
        return cpuid_feature_extract_unsigned_field(isar2,
-                                                   ID_AA64ISAR2_BC_SHIFT);
+                                                   ID_AA64ISAR2_EL1_BC_SHIFT);
 }
 
 const struct cpumask *system_32bit_el0_cpumask(void);

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 495f370156772cf198041e1b89970c589cb22664..0b547f181fb07e90d5ce26082e2f76f2ff8f37f7 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -738,29 +738,29 @@
 #define ID_AA64ISAR1_EL1_GPI_IMP               0x1
 
 /* id_aa64isar2 */
-#define ID_AA64ISAR2_BC_SHIFT          28
-#define ID_AA64ISAR2_APA3_SHIFT                12
-#define ID_AA64ISAR2_GPA3_SHIFT                8
-#define ID_AA64ISAR2_RPRES_SHIFT       4
-#define ID_AA64ISAR2_WFxT_SHIFT                0
+#define ID_AA64ISAR2_EL1_BC_SHIFT              28
+#define ID_AA64ISAR2_EL1_APA3_SHIFT            12
+#define ID_AA64ISAR2_EL1_GPA3_SHIFT            8
+#define ID_AA64ISAR2_EL1_RPRES_SHIFT   4
+#define ID_AA64ISAR2_EL1_WFxT_SHIFT            0
 
 /*
  * Value 0x1 has been removed from the architecture, and is
  * reserved, but has not yet been removed from the ARM ARM
  * as of ARM DDI 0487G.b.
  */
-#define ID_AA64ISAR2_WFxT_NI           0x0
-#define ID_AA64ISAR2_WFxT_IMP          0x2
-
-#define ID_AA64ISAR2_APA3_NI                   0x0
-#define ID_AA64ISAR2_APA3_PAuth                        0x1
-#define ID_AA64ISAR2_APA3_EPAC                 0x2
-#define ID_AA64ISAR2_APA3_PAuth2               0x3
-#define ID_AA64ISAR2_APA3_FPAC                 0x4
-#define ID_AA64ISAR2_APA3_FPACCOMBINE          0x5
-
-#define ID_AA64ISAR2_GPA3_NI                   0x0
-#define ID_AA64ISAR2_GPA3_IMP                  0x1
+#define ID_AA64ISAR2_EL1_WFxT_NI               0x0
+#define ID_AA64ISAR2_EL1_WFxT_IMP              0x2
+
+#define ID_AA64ISAR2_EL1_APA3_NI                       0x0
+#define ID_AA64ISAR2_EL1_APA3_PAuth                    0x1
+#define ID_AA64ISAR2_EL1_APA3_EPAC                     0x2
+#define ID_AA64ISAR2_EL1_APA3_PAuth2                   0x3
+#define ID_AA64ISAR2_EL1_APA3_FPAC                     0x4
+#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE              0x5
+
+#define ID_AA64ISAR2_EL1_GPA3_NI                       0x0
+#define ID_AA64ISAR2_EL1_GPA3_IMP                      0x1
 
 /* id_aa64pfr0 */
 #define ID_AA64PFR0_CSV3_SHIFT         60

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 0d4f0120c51652e113932cfbc3970be2528f3c59..be20100a7d4c595b12152665ef0e2596975ea8b9 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -231,13 +231,13 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 };
 
 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_BC_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
        ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
-                      FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0),
+                      FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
        ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
-                      FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFxT_SHIFT, 4, 0),
+                      FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
@@ -2326,9 +2326,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
                .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
                .sys_reg = SYS_ID_AA64ISAR2_EL1,
                .sign = FTR_UNSIGNED,
-               .field_pos = ID_AA64ISAR2_APA3_SHIFT,
+               .field_pos = ID_AA64ISAR2_EL1_APA3_SHIFT,
                .field_width = 4,
-               .min_field_value = ID_AA64ISAR2_APA3_PAuth,
+               .min_field_value = ID_AA64ISAR2_EL1_APA3_PAuth,
                .matches = has_address_auth_cpucap,
        },
        {
@@ -2364,9 +2364,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
                .type = ARM64_CPUCAP_SYSTEM_FEATURE,
                .sys_reg = SYS_ID_AA64ISAR2_EL1,
                .sign = FTR_UNSIGNED,
-               .field_pos = ID_AA64ISAR2_GPA3_SHIFT,
+               .field_pos = ID_AA64ISAR2_EL1_GPA3_SHIFT,
                .field_width = 4,
-               .min_field_value = ID_AA64ISAR2_GPA3_IMP,
+               .min_field_value = ID_AA64ISAR2_EL1_GPA3_IMP,
                .matches = has_cpuid_feature,
        },
        {
@@ -2516,10 +2516,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
                .type = ARM64_CPUCAP_SYSTEM_FEATURE,
                .sys_reg = SYS_ID_AA64ISAR2_EL1,
                .sign = FTR_UNSIGNED,
-               .field_pos = ID_AA64ISAR2_WFxT_SHIFT,
+               .field_pos = ID_AA64ISAR2_EL1_WFxT_SHIFT,
                .field_width = 4,
                .matches = has_cpuid_feature,
-               .min_field_value = ID_AA64ISAR2_WFxT_IMP,
+               .min_field_value = ID_AA64ISAR2_EL1_WFxT_IMP,
        },
        {},
 };
@@ -2565,8 +2565,8 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
                                  ID_AA64ISAR1_EL1_APA_PAuth)
        },
        {
-               HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT,
-                                 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_PAuth)
+               HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_APA3_SHIFT,
+                                 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_APA3_PAuth)
        },
        {
                HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT,
@@ -2581,8 +2581,8 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
                                  4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP)
        },
        {
-               HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT,
-                                 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_IMP)
+               HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_GPA3_SHIFT,
+                                 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_GPA3_IMP)
        },
        {
                HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT,
@@ -2653,8 +2653,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 #endif /* CONFIG_ARM64_MTE */
        HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
        HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
-       HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
-       HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
+       HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
+       HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
 #ifdef CONFIG_ARM64_SME
        HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME),
        HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),

diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c
index 1a4ebaa315ebb479dda5e644db47651ea9152e15..21b3d03089cabd9b0c37013d993c4e38b37f9ae7 100644 (file)
--- a/arch/arm64/kernel/idreg-override.c
+++ b/arch/arm64/kernel/idreg-override.c
@@ -75,8 +75,8 @@ static const struct ftr_set_desc isar2 __initconst = {
        .name           = "id_aa64isar2",
        .override       = &id_aa64isar2_override,
        .fields         = {
-               { "gpa3", ID_AA64ISAR2_GPA3_SHIFT },
-               { "apa3", ID_AA64ISAR2_APA3_SHIFT },
+               { "gpa3", ID_AA64ISAR2_EL1_GPA3_SHIFT },
+               { "apa3", ID_AA64ISAR2_EL1_APA3_SHIFT },
                {}
        },
 };

diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
index 46cf9dec21ba2e3b01556aa18445835e4428040f..fa6e466ed57f60640d5a502aac53517bbad2d592 100644 (file)
--- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
@@ -193,8 +193,8 @@
        )
 
 #define PVM_ID_AA64ISAR2_ALLOW (\
-       ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3) | \
-       ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) \
+       ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3) | \
+       ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) \
        )
 
 u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id);

diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c
index 5b77bc1cca0cdaebd8468c8115b8a1d83019a0a4..6b94c3e6ff26831d09d1826818d30f290e845962 100644 (file)
--- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c
+++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c
@@ -186,8 +186,8 @@ static u64 get_pvm_id_aa64isar2(const struct kvm_vcpu *vcpu)
        u64 allow_mask = PVM_ID_AA64ISAR2_ALLOW;
 
        if (!vcpu_has_ptrauth(vcpu))
-               allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) |
-                               ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3));
+               allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
+                               ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
 
        return id_aa64isar2_el1_sys_val & allow_mask;
 }

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index ccd973dc346a929a32f4ca2f0813c9a1cc04fbf2..c4fb3874b5e2da6558f1928a0bb5c316268b5af8 100644 (file)
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1143,10 +1143,10 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
                break;
        case SYS_ID_AA64ISAR2_EL1:
                if (!vcpu_has_ptrauth(vcpu))
-                       val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) |
-                                ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3));
+                       val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
+                                ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
                if (!cpus_have_final_cap(ARM64_HAS_WFXT))
-                       val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_WFxT);
+                       val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
                break;
        case SYS_ID_AA64DFR0_EL1:
                /* Limit debug to ARMv8.0 */