addr_code = (base + pdesc->app_resident_code_offset) >> 8;
        addr_data = (base + pdesc->app_resident_data_offset) >> 8;
 
-       memset(desc, 0, sizeof(*desc));
        desc->ctx_dma = FALCON_DMAIDX_UCODE;
        desc->code_dma_base = lower_32_bits(addr_code);
        desc->non_sec_code_off = pdesc->app_resident_code_offset;
                                     &img->lsb_header, sizeof(img->lsb_header));
 
                /* Generate and write BL descriptor */
+               memset(gdesc, 0, ls_func->bl_desc_size);
                ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc);
 
                nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.bl_data_off,
        struct acr_r352_flcn_bl_desc *bl_desc = _bl_desc;
        u64 addr_code, addr_data;
 
-       memset(bl_desc, 0, sizeof(*bl_desc));
        addr_code = offset >> 8;
        addr_data = (offset + hdr->data_dma_base) >> 8;
 
                              code_size, hsbl_desc->start_tag, 0, false);
 
        /* Generate the BL header */
+       memset(bl_desc, 0, bl_desc_size);
        acr->func->generate_hs_bl_desc(load_hdr, bl_desc, offset);
 
        /*
 
        addr_code = base + pdesc->app_resident_code_offset;
        addr_data = base + pdesc->app_resident_data_offset;
 
-       memset(desc, 0, sizeof(*desc));
        desc->ctx_dma = FALCON_DMAIDX_UCODE;
        desc->code_dma_base = u64_to_flcn64(addr_code);
        desc->non_sec_code_off = pdesc->app_resident_code_offset;
 {
        struct acr_r361_flcn_bl_desc *bl_desc = _bl_desc;
 
-       memset(bl_desc, 0, sizeof(*bl_desc));
        bl_desc->ctx_dma = FALCON_DMAIDX_VIRT;
        bl_desc->code_dma_base = u64_to_flcn64(offset);
        bl_desc->non_sec_code_off = hdr->non_sec_code_off;