* level") we need to issue the Set Parameters Commannd
                 * without sleeping (timeout < 0).
                 */
-               err = t4_set_params_timeout(adap, adap->mbox, adap->fn, 0, 1,
+               err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
                                            &name, &value,
                                            -FW_CMD_MAX_TIMEOUT);
 
        int uc_cnt = netdev_uc_count(dev);
        int mc_cnt = netdev_mc_count(dev);
        const struct port_info *pi = netdev_priv(dev);
-       unsigned int mb = pi->adapter->fn;
+       unsigned int mb = pi->adapter->pf;
 
        /* first do the secondary unicast addresses */
        netdev_for_each_uc_addr(ha, dev) {
 
        ret = set_addr_filters(dev, sleep_ok);
        if (ret == 0)
-               ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
+               ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, mtu,
                                    (dev->flags & IFF_PROMISC) ? 1 : 0,
                                    (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
                                    sleep_ok);
 {
        int ret;
        struct port_info *pi = netdev_priv(dev);
-       unsigned int mb = pi->adapter->fn;
+       unsigned int mb = pi->adapter->pf;
 
        /*
         * We do not set address filters and promiscuity here, the stack does
        for (i = 0; i < pi->rss_size; i++, queues++)
                rss[i] = rxq[*queues].rspq.abs_id;
 
-       err = t4_config_rss_range(adapter, adapter->fn, pi->viid, 0,
+       err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
                                  pi->rss_size, rss, pi->rss_size);
        /* If Tunnel All Lookup isn't specified in the global RSS
         * Configuration, then we need to specify a default Ingress
                            FW_PARAMS_PARAM_X_V(
                                        FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
                            FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
-                       err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
-                                           &new_idx);
+                       err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
+                                           &v, &new_idx);
                        if (err)
                                return err;
                }
        if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
                return 0;
 
-       err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
+       err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
                            -1, -1, -1,
                            !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
        if (unlikely(err))
                         u64 *pbar2_qoffset,
                         unsigned int *pbar2_qid)
 {
-       return cxgb4_t4_bar2_sge_qregs(netdev2adap(dev),
+       return t4_bar2_sge_qregs(netdev2adap(dev),
                                 qid,
                                 (qtype == CXGB4_BAR2_QTYPE_EGRESS
                                  ? T4_BAR2_QTYPE_EGRESS
                unsigned int bar2_qid;
                int ret;
 
-               ret = cxgb4_t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
+               ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
                                        &bar2_qoffset, &bar2_qid);
                if (ret)
                        dev_err(adap->pdev_dev, "doorbell drop recovery: "
        unsigned short i;
 
        lli.pdev = adap->pdev;
-       lli.pf = adap->fn;
+       lli.pf = adap->pf;
        lli.l2t = adap->l2t;
        lli.tids = &adap->tids;
        lli.ports = adap->port;
 
        netif_tx_stop_all_queues(dev);
        netif_carrier_off(dev);
-       return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
+       return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
 }
 
 /* Return an error number if the indicated filter isn't writable ...
                } else
                        return -EINVAL;
 
-               mbox = pi->adapter->fn;
+               mbox = pi->adapter->pf;
                if (cmd == SIOCGMIIREG)
                        ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
                                         data->reg_num, &data->val_out);
 
        if (new_mtu < 81 || new_mtu > MAX_MTU)         /* accommodate SACK */
                return -EINVAL;
-       ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
+       ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
                            -1, -1, -1, true);
        if (!ret)
                dev->mtu = new_mtu;
        if (!is_valid_ether_addr(addr->sa_data))
                return -EADDRNOTAVAIL;
 
-       ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
+       ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
                            pi->xact_addr_filt, addr->sa_data, true, true);
        if (ret < 0)
                return ret;
        c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
                               FW_CMD_REQUEST_F | FW_CMD_READ_F);
        c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
-       ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
+       ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
        if (ret < 0)
                return ret;
 
        }
        c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
                               FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
-       ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
+       ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
        if (ret < 0)
                return ret;
 
-       ret = t4_config_glbl_rss(adap, adap->fn,
+       ret = t4_config_glbl_rss(adap, adap->pf,
                                 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
                                 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
                                 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
        if (ret < 0)
                return ret;
 
-       ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, adap->sge.egr_sz, 64,
+       ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
                          MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
                          FW_CMD_CAP_PF);
        if (ret < 0)
        }
 
        /* get basic stuff going */
-       return t4_early_init(adap, adap->fn);
+       return t4_early_init(adap, adap->pf);
 }
 
 /*
                        params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
                             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
                        ret = t4_query_params(adapter, adapter->mbox,
-                                             adapter->fn, 0, 1, params, val);
+                                             adapter->pf, 0, 1, params, val);
                        if (ret == 0) {
                                /*
                                 * For t4_memory_rw() below addresses and
        v =
            FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
            FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
-       ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
+       ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
        if (ret < 0)
                goto bye;
 
                 */
                params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
                             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
-               ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
+               ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
                                      params, val);
 
                /* If the firmware doesn't support Configuration Files,
        params[3] = FW_PARAM_PFVF(FILTER_START);
        params[4] = FW_PARAM_PFVF(FILTER_END);
        params[5] = FW_PARAM_PFVF(IQFLINT_START);
-       ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
+       ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
        if (ret < 0)
                goto bye;
        adap->sge.egr_start = val[0];
         */
        params[0] = FW_PARAM_PFVF(EQ_END);
        params[1] = FW_PARAM_PFVF(IQFLINT_END);
-       ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
+       ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
        if (ret < 0)
                goto bye;
        adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
 
        params[0] = FW_PARAM_PFVF(CLIP_START);
        params[1] = FW_PARAM_PFVF(CLIP_END);
-       ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
+       ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
        if (ret < 0)
                goto bye;
        adap->clipt_start = val[0];
        /* query params related to active filter region */
        params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
        params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
-       ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
+       ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
        /* If Active filter size is set we enable establishing
         * offload connection through firmware work request
         */
         */
        params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
        val[0] = 1;
-       (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
+       (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
 
        /*
         * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
                adap->params.ulptx_memwrite_dsgl = false;
        } else {
                params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
-               ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
+               ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
                                      1, params, val);
                adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
        }
                params[3] = FW_PARAM_PFVF(TDDP_START);
                params[4] = FW_PARAM_PFVF(TDDP_END);
                params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
-               ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
+               ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
                                      params, val);
                if (ret < 0)
                        goto bye;
                params[3] = FW_PARAM_PFVF(RQ_END);
                params[4] = FW_PARAM_PFVF(PBL_START);
                params[5] = FW_PARAM_PFVF(PBL_END);
-               ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
+               ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
                                      params, val);
                if (ret < 0)
                        goto bye;
                params[3] = FW_PARAM_PFVF(CQ_END);
                params[4] = FW_PARAM_PFVF(OCQ_START);
                params[5] = FW_PARAM_PFVF(OCQ_END);
-               ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params,
+               ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
                                      val);
                if (ret < 0)
                        goto bye;
 
                params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
                params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
-               ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params,
+               ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
                                      val);
                if (ret < 0) {
                        adap->params.max_ordird_qp = 8;
        if (caps_cmd.iscsicaps) {
                params[0] = FW_PARAM_PFVF(ISCSI_START);
                params[1] = FW_PARAM_PFVF(ISCSI_END);
-               ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
+               ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
                                      params, val);
                if (ret < 0)
                        goto bye;
 
        if (t4_wait_dev_ready(adap->regs) < 0)
                return PCI_ERS_RESULT_DISCONNECT;
-       if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
+       if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
                return PCI_ERS_RESULT_DISCONNECT;
        adap->flags |= FW_OK;
        if (adap_init1(adap, &c))
        for_each_port(adap, i) {
                struct port_info *p = adap2pinfo(adap, i);
 
-               ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
+               ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1,
                                  NULL, NULL);
                if (ret < 0)
                        return PCI_ERS_RESULT_DISCONNECT;
                        free_netdev(adapter->port[i]);
                }
        if (adapter->flags & FW_OK)
-               t4_fw_bye(adapter, adapter->fn);
+               t4_fw_bye(adapter, adapter->pf);
 }
 
 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
        adapter->pdev = pdev;
        adapter->pdev_dev = &pdev->dev;
        adapter->mbox = func;
-       adapter->fn = func;
+       adapter->pf = func;
        adapter->msg_enable = dflt_msg_enable;
        memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
 
        if (!is_t4(adapter->params.chip)) {
                s_qpp = (QUEUESPERPAGEPF0_S +
                        (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
-                       adapter->fn);
+                       adapter->pf);
                qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
                      SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
                num_seg = PAGE_SIZE / SEGMENT_SIZE;
 
 
        cpl->ctrl0 = htonl(TXPKT_OPCODE_V(CPL_TX_PKT_XT) |
                           TXPKT_INTF_V(pi->tx_chan) |
-                          TXPKT_PF_V(adap->fn));
+                          TXPKT_PF_V(adap->pf));
        cpl->pack = htons(0);
        cpl->len = htons(skb->len);
        cpl->ctrl1 = cpu_to_be64(cntrl);
        u64 bar2_qoffset;
        int ret;
 
-       ret = cxgb4_t4_bar2_sge_qregs(adapter, qid, qtype,
+       ret = t4_bar2_sge_qregs(adapter, qid, qtype,
                                &bar2_qoffset, pbar2_qid);
        if (ret)
                return NULL;
        memset(&c, 0, sizeof(c));
        c.op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
                            FW_CMD_WRITE_F | FW_CMD_EXEC_F |
-                           FW_IQ_CMD_PFN_V(adap->fn) | FW_IQ_CMD_VFN_V(0));
+                           FW_IQ_CMD_PFN_V(adap->pf) | FW_IQ_CMD_VFN_V(0));
        c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC_F | FW_IQ_CMD_IQSTART_F |
                                 FW_LEN16(c));
        c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE_V(FW_IQ_TYPE_FL_INT_CAP) |
                c.fl0addr = cpu_to_be64(fl->addr);
        }
 
-       ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
+       ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
        if (ret)
                goto err;
 
                                             CONMCTXT_CNGCHMAP_V(1 << (i << 2));
                        }
                }
-               ret = t4_set_params(adap, adap->mbox, adap->fn, 0, 1,
+               ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
                                    ¶m, &val);
                if (ret)
                        dev_warn(adap->pdev_dev, "Failed to set Congestion"
        memset(&c, 0, sizeof(c));
        c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD) | FW_CMD_REQUEST_F |
                            FW_CMD_WRITE_F | FW_CMD_EXEC_F |
-                           FW_EQ_ETH_CMD_PFN_V(adap->fn) |
+                           FW_EQ_ETH_CMD_PFN_V(adap->pf) |
                            FW_EQ_ETH_CMD_VFN_V(0));
        c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC_F |
                                 FW_EQ_ETH_CMD_EQSTART_F | FW_LEN16(c));
                      FW_EQ_ETH_CMD_EQSIZE_V(nentries));
        c.eqaddr = cpu_to_be64(txq->q.phys_addr);
 
-       ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
+       ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
        if (ret) {
                kfree(txq->q.sdesc);
                txq->q.sdesc = NULL;
 
        c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST_F |
                            FW_CMD_WRITE_F | FW_CMD_EXEC_F |
-                           FW_EQ_CTRL_CMD_PFN_V(adap->fn) |
+                           FW_EQ_CTRL_CMD_PFN_V(adap->pf) |
                            FW_EQ_CTRL_CMD_VFN_V(0));
        c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC_F |
                                 FW_EQ_CTRL_CMD_EQSTART_F | FW_LEN16(c));
                      FW_EQ_CTRL_CMD_EQSIZE_V(nentries));
        c.eqaddr = cpu_to_be64(txq->q.phys_addr);
 
-       ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
+       ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
        if (ret) {
                dma_free_coherent(adap->pdev_dev,
                                  nentries * sizeof(struct tx_desc),
        memset(&c, 0, sizeof(c));
        c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST_F |
                            FW_CMD_WRITE_F | FW_CMD_EXEC_F |
-                           FW_EQ_OFLD_CMD_PFN_V(adap->fn) |
+                           FW_EQ_OFLD_CMD_PFN_V(adap->pf) |
                            FW_EQ_OFLD_CMD_VFN_V(0));
        c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC_F |
                                 FW_EQ_OFLD_CMD_EQSTART_F | FW_LEN16(c));
                      FW_EQ_OFLD_CMD_EQSIZE_V(nentries));
        c.eqaddr = cpu_to_be64(txq->q.phys_addr);
 
-       ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
+       ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
        if (ret) {
                kfree(txq->q.sdesc);
                txq->q.sdesc = NULL;
        unsigned int fl_id = fl ? fl->cntxt_id : 0xffff;
 
        adap->sge.ingr_map[rq->cntxt_id - adap->sge.ingr_start] = NULL;
-       t4_iq_free(adap, adap->fn, adap->fn, 0, FW_IQ_TYPE_FL_INT_CAP,
+       t4_iq_free(adap, adap->mbox, adap->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
                   rq->cntxt_id, fl_id, 0xffff);
        dma_free_coherent(adap->pdev_dev, (rq->size + 1) * rq->iqe_len,
                          rq->desc, rq->phys_addr);
                        free_rspq_fl(adap, &eq->rspq,
                                     eq->fl.size ? &eq->fl : NULL);
                if (etq->q.desc) {
-                       t4_eth_eq_free(adap, adap->fn, adap->fn, 0,
+                       t4_eth_eq_free(adap, adap->mbox, adap->pf, 0,
                                       etq->q.cntxt_id);
                        free_tx_desc(adap, &etq->q, etq->q.in_use, true);
                        kfree(etq->q.sdesc);
 
                if (q->q.desc) {
                        tasklet_kill(&q->qresume_tsk);
-                       t4_ofld_eq_free(adap, adap->fn, adap->fn, 0,
+                       t4_ofld_eq_free(adap, adap->mbox, adap->pf, 0,
                                        q->q.cntxt_id);
                        free_tx_desc(adap, &q->q, q->q.in_use, false);
                        kfree(q->q.sdesc);
 
                if (cq->q.desc) {
                        tasklet_kill(&cq->qresume_tsk);
-                       t4_ctrl_eq_free(adap, adap->fn, adap->fn, 0,
+                       t4_ctrl_eq_free(adap, adap->mbox, adap->pf, 0,
                                        cq->q.cntxt_id);
                        __skb_queue_purge(&cq->sendq);
                        free_txq(adap, &cq->q);
 
  */
 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 {
-       u32 req = ENABLE_F | FUNCTION_V(adap->fn) | REGISTER_V(reg);
+       u32 req = ENABLE_F | FUNCTION_V(adap->pf) | REGISTER_V(reg);
 
        if (is_t4(adap->params.chip))
                req |= LOCALCFG_F;
        mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
        if (is_t4(adap->params.chip))
                mem_base -= adap->t4_bar0;
-       win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->fn);
+       win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 
        /* Calculate our initial PCI-E Memory Window Position and Offset into
         * that Window.
        ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
        ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
        ldst_cmd.u.pcie.ctrl_to_fn =
-               (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->fn));
+               (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
        ldst_cmd.u.pcie.r = reg;
 
        /* If the LDST Command succeeds, return the result, otherwise
                 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
                 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
                 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
-       ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
+       ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
                              ¶m, &val);
        if (ret < 0)
                return ret;
                 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
                 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
        val = phy_fw_size;
-       ret = t4_query_params_rw(adap, adap->mbox, adap->fn, 0, 1,
+       ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
                                 ¶m, &val, 1);
        if (ret < 0)
                return ret;
                 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
                 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
                 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
-       ret = t4_set_params_timeout(adap, adap->mbox, adap->fn, 0, 1,
+       ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
                                    ¶m, &val, 30000);
 
        /* If we have version number support, then check to see that the new
        c.op_to_vfn =
                cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
                            FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
-                           FW_PARAMS_CMD_PFN_V(adap->fn) |
+                           FW_PARAMS_CMD_PFN_V(adap->pf) |
                            FW_PARAMS_CMD_VFN_V(0));
        c.retval_len16 = cpu_to_be32(FW_LEN16(c));
        c.param[0].mnem =
 }
 
 /**
- *     cxgb4_t4_bar2_sge_qregs - return BAR2 SGE Queue register information
+ *     t4_bar2_sge_qregs - return BAR2 SGE Queue register information
  *     @adapter: the adapter
  *     @qid: the Queue ID
  *     @qtype: the Ingress or Egress type for @qid
  *     Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
  *     then these "Inferred Queue ID" register may not be used.
  */
-int cxgb4_t4_bar2_sge_qregs(struct adapter *adapter,
+int t4_bar2_sge_qregs(struct adapter *adapter,
                      unsigned int qid,
                      enum t4_bar2_qtype qtype,
                      u64 *pbar2_qoffset,
         */
        hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
        s_hps = (HOSTPAGESIZEPF0_S +
-                (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->fn);
+                (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
        sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
 
        /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
         */
        s_qpp = (QUEUESPERPAGEPF0_S +
-               (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->fn);
+               (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
        qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
        sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
        qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);