drm_crtc_vblank_put(crtc);
 }
 
-struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915)
+struct intel_crtc *intel_first_crtc(struct intel_display *display)
 {
-       return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0));
+       return to_intel_crtc(drm_crtc_from_index(display->drm, 0));
 }
 
 struct intel_crtc *intel_crtc_for_pipe(struct intel_display *display,
        drm_crtc_wait_one_vblank(&crtc->base);
 }
 
-void intel_wait_for_vblank_if_active(struct drm_i915_private *i915,
+void intel_wait_for_vblank_if_active(struct intel_display *display,
                                     enum pipe pipe)
 {
-       struct intel_display *display = &i915->display;
        struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
 
        if (crtc->active)
 
 u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
 {
-       struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+       struct intel_display *display = to_intel_display(crtc_state);
 
        /*
         * From Gen 11, in case of dsi cmd mode, frame counter wouldn't
         * On i965gm the hardware frame counter reads
         * zero when the TV encoder is enabled :(
         */
-       if (IS_I965GM(dev_priv) &&
+       if (display->platform.i965gm &&
            (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
                return 0;
 
-       if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
+       if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
                return 0xffffffff; /* full 32 bit counter */
-       else if (DISPLAY_VER(dev_priv) >= 3)
+       else if (DISPLAY_VER(display) >= 3)
                return 0xffffff; /* only 24 bits of frame count */
        else
                return 0; /* Gen2 doesn't have a hardware frame counter */
 
 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
 {
+       struct intel_display *display = to_intel_display(crtc_state);
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-       struct intel_display *display = to_intel_display(crtc);
 
        /*
         * Should really happen exactly when we disable the pipe
        .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
 };
 
-int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
+int intel_crtc_init(struct intel_display *display, enum pipe pipe)
 {
+       struct drm_i915_private *dev_priv = to_i915(display->drm);
        struct intel_plane *primary, *cursor;
        const struct drm_crtc_funcs *funcs;
        struct intel_crtc *crtc;
                return PTR_ERR(crtc);
 
        crtc->pipe = pipe;
-       crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe];
+       crtc->num_scalers = DISPLAY_RUNTIME_INFO(display)->num_scalers[pipe];
 
-       if (DISPLAY_VER(dev_priv) >= 9)
+       if (DISPLAY_VER(display) >= 9)
                primary = skl_universal_plane_create(dev_priv, pipe, PLANE_1);
        else
                primary = intel_primary_plane_create(dev_priv, pipe);
 
        intel_init_fifo_underrun_reporting(dev_priv, crtc, false);
 
-       for_each_sprite(dev_priv, pipe, sprite) {
+       for_each_sprite(display, pipe, sprite) {
                struct intel_plane *plane;
 
                if (DISPLAY_VER(dev_priv) >= 9)
        }
        crtc->plane_ids_mask |= BIT(cursor->id);
 
-       if (HAS_GMCH(dev_priv)) {
-               if (IS_CHERRYVIEW(dev_priv) ||
-                   IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
+       if (HAS_GMCH(display)) {
+               if (display->platform.cherryview ||
+                   display->platform.valleyview ||
+                   display->platform.g4x)
                        funcs = &g4x_crtc_funcs;
-               else if (DISPLAY_VER(dev_priv) == 4)
+               else if (DISPLAY_VER(display) == 4)
                        funcs = &i965_crtc_funcs;
-               else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
+               else if (display->platform.i945gm ||
+                        display->platform.i915gm)
                        funcs = &i915gm_crtc_funcs;
-               else if (DISPLAY_VER(dev_priv) == 3)
+               else if (DISPLAY_VER(display) == 3)
                        funcs = &i915_crtc_funcs;
                else
                        funcs = &i8xx_crtc_funcs;
        } else {
-               if (DISPLAY_VER(dev_priv) >= 8)
+               if (DISPLAY_VER(display) >= 8)
                        funcs = &bdw_crtc_funcs;
                else
                        funcs = &ilk_crtc_funcs;
        }
 
-       ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
+       ret = drm_crtc_init_with_planes(display->drm, &crtc->base,
                                        &primary->base, &cursor->base,
                                        funcs, "pipe %c", pipe_name(pipe));
        if (ret)
                goto fail;
 
-       if (DISPLAY_VER(dev_priv) >= 11)
+       if (DISPLAY_VER(display) >= 11)
                drm_crtc_create_scaling_filter_property(&crtc->base,
                                                BIT(DRM_SCALING_FILTER_DEFAULT) |
                                                BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
 
        cpu_latency_qos_add_request(&crtc->vblank_pm_qos, PM_QOS_DEFAULT_VALUE);
 
-       drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
+       drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
 
        return 0;
 
 void intel_pipe_update_start(struct intel_atomic_state *state,
                             struct intel_crtc *crtc)
 {
-       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       struct intel_display *display = to_intel_display(state);
        const struct intel_crtc_state *old_crtc_state =
                intel_atomic_get_old_crtc_state(state, crtc);
        struct intel_crtc_state *new_crtc_state =
 
        intel_vblank_evade_init(old_crtc_state, new_crtc_state, &evade);
 
-       if (drm_WARN_ON(&dev_priv->drm, drm_crtc_vblank_get(&crtc->base)))
+       if (drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base)))
                goto irq_disable;
 
        /*
 void intel_pipe_update_end(struct intel_atomic_state *state,
                           struct intel_crtc *crtc)
 {
+       struct intel_display *display = to_intel_display(state);
        struct intel_crtc_state *new_crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        enum pipe pipe = crtc->pipe;
         * Incase of mipi dsi command mode, we need to set frame update
         * request for every commit.
         */
-       if (DISPLAY_VER(dev_priv) >= 11 &&
+       if (DISPLAY_VER(display) >= 11 &&
            intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
                icl_dsi_frame_update(new_crtc_state);
 
 
        if (crtc->debug.start_vbl_count &&
            crtc->debug.start_vbl_count != end_vbl_count) {
-               drm_err(&dev_priv->drm,
+               drm_err(display->drm,
                        "Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
                        pipe_name(pipe), crtc->debug.start_vbl_count,
                        end_vbl_count,