Merge tag 'spi-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown:
 "A fairly quiet release for SPI, nothing really going on in the core
  although there's been quite a bit of driver related activity.

  This includes the addition of some shared code in drivers/memory for
  the Renesas RPC-IF which is used by a newly added SPI driver, the
  memory subsystem doesn't seem to have a fixed maintainer at the minute
  and this seemed like the most sensible way to get that hardware
  supported.

   - Quite a few cleanups and optimizations for the Altera, Qualcomm
     GENI, sun6i and lantiq drivers.

   - Several more GPIO descriptor conversions.

   - Move the Cadence QuadSPI driver from drivers/mtd to drivers/spi.

   - New support for Mediatek MT8192 and Renesas RPC-IF, R8A7742 and
     R8A774e1"

* tag 'spi-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (119 commits)
  dt-bindings: lpspi: New property in document DT bindings for LPSPI
  spi: lpspi: fix using CS discontinuously on i.MX8DXLEVK
  spi: lpspi: remove unused fsl_lpspi->chipselect
  spi: lpspi: Fix kernel warning dump when probe fail after calling spi_register
  spi: rockchip: Fix error in SPI slave pio read
  spi: rockchip: Support 64-location deep FIFOs
  spi: rockchip: Config spi rx dma burst size depend on xfer length
  spi: spi-topcliff-pch: drop call to wakeup-disable
  spi: spidev: Align buffers for DMA
  spi: correct kernel-doc inconsistency
  spi: sun4i: update max transfer size reported
  spi: imx: enable runtime pm support
  spi: update bindings for MT8192 SoC
  spi: mediatek: add spi support for mt8192 IC
  spi: Add bindings for Lightning Mountain SoC
  spi: lantiq: Add support to Lightning Mountain SoC
  spi: lantiq: Move interrupt configuration to SoC specific data structure
  spi: lantiq: Add fifo size bit mask in SoC specific data structure
  spi: lantiq: Add support to acknowledge interrupt
  spi: lantiq: Move interrupt control register offesets to SoC specific data structure
  ...

diff --cc drivers/memory/Kconfig
Simple merge

diff --cc drivers/spi/spi-geni-qcom.c
index 7a88cc03600420262fcf0101b1e9d057640fe2a2,1d96a7f32fda75b5afded3503582ee99e8eb9bf3..80cea5cd361292604ba3fb52583a9f82222ef99f
--- 1/drivers/spi/spi-geni-qcom.c
--- 2/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@@ -331,8 -308,22 +333,23 @@@ static void setup_fifo_xfer(struct spi_
        u32 m_cmd = 0;
        u32 spi_tx_cfg, len;
        struct geni_se *se = &mas->se;
 +      int ret;
  
+       /*
+        * Ensure that our interrupt handler isn't still running from some
+        * prior command before we start messing with the hardware behind
+        * its back.  We don't need to _keep_ the lock here since we're only
+        * worried about racing with out interrupt handler.  The SPI core
+        * already handles making sure that we're not trying to do two
+        * transfers at once or setting a chip select and doing a transfer
+        * concurrently.
+        *
+        * NOTE: we actually _can't_ hold the lock here because possibly we
+        * might call clk_set_rate() which needs to be able to sleep.
+        */
+       spin_lock_irq(&mas->lock);
+       spin_unlock_irq(&mas->lock);
+ 
        spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
        if (xfer->bits_per_word != mas->cur_bits_per_word) {
                spi_setup_word_len(mas, mode, xfer->bits_per_word);
@@@ -591,21 -615,14 +632,25 @@@ static int spi_geni_probe(struct platfo
        spi->handle_err = handle_fifo_timeout;
        spi->set_cs = spi_geni_set_cs;
  
-       init_completion(&mas->xfer_done);
+       init_completion(&mas->cs_done);
+       init_completion(&mas->cancel_done);
+       init_completion(&mas->abort_done);
        spin_lock_init(&mas->lock);
+       pm_runtime_use_autosuspend(&pdev->dev);
+       pm_runtime_set_autosuspend_delay(&pdev->dev, 250);
        pm_runtime_enable(dev);
  
 +      ret = geni_icc_get(&mas->se, NULL);
 +      if (ret)
 +              goto spi_geni_probe_runtime_disable;
 +      /* Set the bus quota to a reasonable value for register access */
 +      mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
 +      mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
 +
 +      ret = geni_icc_set_bw(&mas->se);
 +      if (ret)
 +              goto spi_geni_probe_runtime_disable;
 +
        ret = spi_geni_init(mas);
        if (ret)
                goto spi_geni_probe_runtime_disable;