IS_HASWELL(dev_priv))
 #define HAS_DP_MST(dev_priv)            (HAS_DDI(dev_priv))
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
-#define HAS_PSR(dev_priv)               (INTEL_INFO(dev_priv)->display.has_psr)
+#define HAS_PSR(dev_priv)               (DISPLAY_VER(dev_priv) >= 9)
 #define HAS_PSR_HW_TRACKING(dev_priv) \
        (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(dev_priv)    (DISPLAY_VER(dev_priv) >= 12)
 
        .display.has_dmc = 1, \
        .display.has_hdcp = 1, \
        .display.has_ipc = 1, \
-       .display.has_psr = 1, \
        .display.has_psr_hw_tracking = 1, \
        .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
        .dbuf.slice_mask = BIT(DBUF_S1)
        .display.has_fpga_dbg = 1, \
        .display.fbc_mask = BIT(INTEL_FBC_A), \
        .display.has_hdcp = 1, \
-       .display.has_psr = 1, \
        .display.has_psr_hw_tracking = 1, \
        .has_runtime_pm = 1, \
        .display.has_dmc = 1, \
        .display.has_hdcp = 1,                                                  \
        .display.has_hotplug = 1,                                               \
        .display.has_ipc = 1,                                                   \
-       .display.has_psr = 1,                                                   \
        .display.ver = 13,                                                      \
        .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),     \
        .pipe_offsets = {                                                       \