serial: core: fix tcdrain() with CTS enabled

Do not set timeout to twice the approximate amount of time to send the
entire FIFO if CTS is enabled. If the caller requested no timeout, e.g.
when userspace program called tcdrain(), then wait without any timeout.

Premature return from tcdrain() was observed on imx based system which
has 32 character long transmitter FIFO with hardware CTS handling.

Simple userspace application that reproduces problem has to:
  * Open tty device, enable hardware flow control (CRTSCTS)
  * Write data, e.g. 26 bytes
  * Call tcdrain() to wait for the transmitter
  * Close tty device

The other side of serial connection has to:
  * Receive some data, e.g. 10 bytes
  * Set RTS output (CTS input from sender perspective) inactive for
    at least twice the port timeout
  * Try to receive remaining data

Without this patch, userspace application will finish without any error
while the other side of connection will never receive remaining data.

Signed-off-by: Tomasz Moń <tomasz.mon@camlingroup.com>
Link: https://lore.kernel.org/r/20220228054911.1420221-1-tomasz.mon@camlingroup.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index d067b44f1425a4873a1b34926db93c9fc750ed56..01823ce87801960356ed8e6a8bf0d24b815223b0 100644 (file)
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -1650,17 +1650,19 @@ static void uart_wait_until_sent(struct tty_struct *tty, int timeout)
        if (timeout && timeout < char_time)
                char_time = timeout;
 
-       /*
-        * If the transmitter hasn't cleared in twice the approximate
-        * amount of time to send the entire FIFO, it probably won't
-        * ever clear.  This assumes the UART isn't doing flow
-        * control, which is currently the case.  Hence, if it ever
-        * takes longer than port->timeout, this is probably due to a
-        * UART bug of some kind.  So, we clamp the timeout parameter at
-        * 2*port->timeout.
-        */
-       if (timeout == 0 || timeout > 2 * port->timeout)
-               timeout = 2 * port->timeout;
+       if (!uart_cts_enabled(port)) {
+               /*
+                * If the transmitter hasn't cleared in twice the approximate
+                * amount of time to send the entire FIFO, it probably won't
+                * ever clear.  This assumes the UART isn't doing flow
+                * control, which is currently the case.  Hence, if it ever
+                * takes longer than port->timeout, this is probably due to a
+                * UART bug of some kind.  So, we clamp the timeout parameter at
+                * 2*port->timeout.
+                */
+               if (timeout == 0 || timeout > 2 * port->timeout)
+                       timeout = 2 * port->timeout;
+       }
 
        expire = jiffies + timeout;
 
@@ -1676,7 +1678,7 @@ static void uart_wait_until_sent(struct tty_struct *tty, int timeout)
                msleep_interruptible(jiffies_to_msecs(char_time));
                if (signal_pending(current))
                        break;
-               if (time_after(jiffies, expire))
+               if (timeout && time_after(jiffies, expire))
                        break;
        }
        uart_port_deref(port);