},
 };
 
-static struct clk_branch gcc_hmss_dvm_bus_clk = {
-       .halt_reg = 0x4808c,
-       .halt_check = BRANCH_HALT,
-       .clkr = {
-               .enable_reg = 0x4808c,
-               .enable_mask = BIT(0),
-               .hw.init = &(struct clk_init_data){
-                       .name = "gcc_hmss_dvm_bus_clk",
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
 static struct clk_branch gcc_hmss_rbcpr_clk = {
        .halt_reg = 0x48008,
        .halt_check = BRANCH_HALT,
        },
 };
 
-static struct clk_branch gcc_lpass_at_clk = {
-       .halt_reg = 0x47020,
-       .halt_check = BRANCH_HALT,
-       .clkr = {
-               .enable_reg = 0x47020,
-               .enable_mask = BIT(0),
-               .hw.init = &(struct clk_init_data){
-                       .name = "gcc_lpass_at_clk",
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
 static struct clk_branch gcc_lpass_trig_clk = {
        .halt_reg = 0x4701c,
        .halt_check = BRANCH_HALT,
        [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
        [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
        [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
-       [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
        [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
        [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,
-       [GCC_LPASS_AT_CLK] = &gcc_lpass_at_clk.clkr,
        [GCC_LPASS_TRIG_CLK] = &gcc_lpass_trig_clk.clkr,
        [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
        [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,