}
 
 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,
-                              int status, int tag, bool gn)
+                              int status, int tag, u8 gn)
 {
        memset(cmd, 0, sizeof(*cmd));
 
        struct iommu_cmd cmd;
        int qdep;
 
-       qdep     = dev_data->ats.qdep;
+       qdep     = dev_data->ats_qdep;
        iommu    = rlookup_amd_iommu(dev_data->dev);
        if (!iommu)
                return -EINVAL;
                        return ret;
        }
 
-       if (dev_data->ats.enabled)
+       if (dev_data->ats_enabled)
                ret = device_flush_iotlb(dev_data, 0, ~0UL);
 
        return ret;
 
        list_for_each_entry(dev_data, &domain->dev_list, list) {
 
-               if (!dev_data->ats.enabled)
+               if (!dev_data->ats_enabled)
                        continue;
 
                ret |= device_flush_iotlb(dev_data, address, size);
        iommu = rlookup_amd_iommu(dev_data->dev);
        if (!iommu)
                return;
-       ats   = dev_data->ats.enabled;
+       ats   = dev_data->ats_enabled;
 
        /* Update data structures */
        dev_data->domain = domain;
                        if (pdev_pri_ats_enable(pdev) != 0)
                                goto out;
 
-                       dev_data->ats.enabled = true;
-                       dev_data->ats.qdep    = pci_ats_queue_depth(pdev);
+                       dev_data->ats_enabled = 1;
+                       dev_data->ats_qdep    = pci_ats_queue_depth(pdev);
                        dev_data->pri_tlp     = pci_prg_resp_pasid_required(pdev);
                }
        } else if (amd_iommu_iotlb_sup &&
                   pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
-               dev_data->ats.enabled = true;
-               dev_data->ats.qdep    = pci_ats_queue_depth(pdev);
+               dev_data->ats_enabled = 1;
+               dev_data->ats_qdep    = pci_ats_queue_depth(pdev);
        }
 
 skip_ats_check:
 
        if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
                pdev_iommuv2_disable(to_pci_dev(dev));
-       else if (dev_data->ats.enabled)
+       else if (dev_data->ats_enabled)
                pci_disable_ats(to_pci_dev(dev));
 
-       dev_data->ats.enabled = false;
+       dev_data->ats_enabled = 0;
 
 out:
        spin_unlock(&dev_data->lock);
                if (!iommu)
                        continue;
                set_dte_entry(iommu, dev_data->devid, domain,
-                             dev_data->ats.enabled, dev_data->iommu_v2);
+                             dev_data->ats_enabled, dev_data->iommu_v2);
                clone_aliases(iommu, dev_data->dev);
        }
 }
                   There might be non-IOMMUv2 capable devices in an IOMMUv2
                 * domain.
                 */
-               if (!dev_data->ats.enabled)
+               if (!dev_data->ats_enabled)
                        continue;
 
-               qdep  = dev_data->ats.qdep;
+               qdep  = dev_data->ats_qdep;
                iommu = rlookup_amd_iommu(dev_data->dev);
                if (!iommu)
                        continue;