]> www.infradead.org Git - users/hch/misc.git/commitdiff
net: ena: cosmetic: minor code changes
authorArthur Kiyanovski <akiyano@amazon.com>
Fri, 22 May 2020 09:09:04 +0000 (12:09 +0300)
committerDavid S. Miller <davem@davemloft.net>
Fri, 22 May 2020 21:12:48 +0000 (14:12 -0700)
1. Use BIT macro instead of shift operator for code clarity
2. Replace multiple flag assignments to a single assignment of multiple
   flags in ena_com_add_single_rx_desc()
3. Move ENA_HASH_KEY_SIZE from ena_netdev.h to ena_com.h

Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/amazon/ena/ena_com.c
drivers/net/ethernet/amazon/ena/ena_com.h
drivers/net/ethernet/amazon/ena/ena_eth_com.c
drivers/net/ethernet/amazon/ena/ena_netdev.h

index bf3465e5a2e7191e13ca19e6b9071466f1bc8503..4b1dbedbe92107a7e8913760a6f647fdeaa58471 100644 (file)
@@ -2285,7 +2285,7 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
        if (unlikely(rc))
                return rc;
 
-       if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) {
+       if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
                pr_err("Flow hash function %d isn't supported\n", func);
                return -EOPNOTSUPP;
        }
index bd65ae205f8d204d4bc2f7c65f01d64d415e26fe..325c9a5f677b0fb0befe01b57921afd120d4c462 100644 (file)
@@ -77,6 +77,8 @@
 #define ENA_INTR_INITIAL_RX_INTERVAL_USECS 0
 #define ENA_DEFAULT_INTR_DELAY_RESOLUTION 1
 
+#define ENA_HASH_KEY_SIZE 40
+
 #define ENA_HW_HINTS_NO_TIMEOUT        0xFFFF
 
 #define ENA_FEATURE_MAX_QUEUE_EXT_VER 1
index a014f514c06907ac7f35f49eddb19a27bc8bed48..ec8ea25e988de48f3615df9e07cac2ed50eaf279 100644 (file)
@@ -584,10 +584,10 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 
        desc->length = ena_buf->len;
 
-       desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK;
-       desc->ctrl |= ENA_ETH_IO_RX_DESC_LAST_MASK;
-       desc->ctrl |= io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK;
-       desc->ctrl |= ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;
+       desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK |
+               ENA_ETH_IO_RX_DESC_LAST_MASK |
+               (io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK) |
+               ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;
 
        desc->req_id = req_id;
 
index 5320b916a36b66ce97ac579624a35e2b97704017..9b3948c7e8a06fa044b534f3edf7151be10fed76 100644 (file)
@@ -98,8 +98,6 @@
 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
 #define ENA_RX_RSS_TABLE_SIZE  (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
 
-#define ENA_HASH_KEY_SIZE      40
-
 /* The number of tx packet completions that will be handled each NAPI poll
  * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER.
  */