arm64: dts: imx8mn-beacon: Configure Ethernet PHY reset and GPIO IRQ

The Ethernet PHY setup currently assumes that the bootloader will take the
PHY out of reset, but this behavior is not guaranteed across all
bootloaders. Add the reset GPIO to ensure the kernel can properly control
the PHY reset line.

Also configure the PHY IRQ GPIO to enable interrupt-driven link status
reporting, instead of relying on polling.

This ensures more reliable Ethernet initialization and improves PHY event
handling.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
index bb11590473a4c7c90471d07ae7a7ce8e04b1799f..b3692b367a42acc49cc486c7478cfdcf20f03e1d 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
@@ -88,6 +88,9 @@
                ethphy0: ethernet-phy@0 {
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <0>;
+                       reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+                       interrupt-parent = <&gpio1>;
+                       interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
                };
        };
 };
@@ -326,6 +329,7 @@
                        MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
                        MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
                        MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
+                       MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10             0x146
                        MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
                >;
        };