acpi_handle chandle, handle;
        struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
 
-       /*
-        * Per PCI firmware specification, we should run the ACPI _OSC
-        * method to get control of hotplug hardware before using it. If
-        * an _OSC is missing, we look for an OSHP to do the same thing.
-        * To handle different BIOS behavior, we look for _OSC on a root
-        * bridge preferentially (according to PCI fw spec). Later for
-        * OSHP within the scope of the hotplug controller and its parents,
-        * up to the host bridge under which this controller exists.
-        */
-       if (shpchp_is_native(pdev))
-               return 0;
-
-       /* If _OSC exists, we should not evaluate OSHP */
-
        /*
         * If there's no ACPI host bridge (i.e., ACPI support is compiled
         * into the kernel but the hardware platform doesn't support ACPI),
        if (!root)
                return 0;
 
-       if (root->osc_support_set)
-               goto no_control;
+       /*
+        * If _OSC exists, it determines whether we're allowed to manage
+        * the SHPC.  We executed it while enumerating the host bridge.
+        */
+       if (root->osc_support_set) {
+               if (host->native_shpc_hotplug)
+                       return 0;
+               return -ENODEV;
+       }
 
+       /*
+        * In the absence of _OSC, we're always allowed to manage the SHPC.
+        * However, if an OSHP method is present, we must execute it so the
+        * firmware can transfer control to the OS, e.g., direct interrupts
+        * to the OS instead of to the firmware.
+        *
+        * N.B. The PCI Firmware Spec (r3.2, sec 4.8) does not endorse
+        * searching up the ACPI hierarchy, so the loops below are suspect.
+        */
        handle = ACPI_HANDLE(&pdev->dev);
        if (!handle) {
                /*
                if (ACPI_FAILURE(status))
                        break;
        }
-no_control:
+
        pci_info(pdev, "Cannot get control of SHPC hotplug\n");
        kfree(string.pointer);
        return -ENODEV;
 
        return 0;
 }
 
+static bool shpc_capable(struct pci_dev *bridge)
+{
+       /*
+        * It is assumed that AMD GOLAM chips support SHPC but they do not
+        * have SHPC capability.
+        */
+       if (bridge->vendor == PCI_VENDOR_ID_AMD &&
+           bridge->device == PCI_DEVICE_ID_AMD_GOLAM_7450)
+               return true;
+
+       if (pci_find_capability(bridge, PCI_CAP_ID_SHPC))
+               return true;
+
+       return false;
+}
+
 static int shpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
        int rc;
        struct controller *ctrl;
 
+       if (!shpc_capable(pdev))
+               return -ENODEV;
+
        if (acpi_get_hp_hw_control_from_firmware(pdev))
                return -ENODEV;
 
        if (rc)
                goto err_cleanup_slots;
 
+       pdev->shpc_managed = 1;
        return 0;
 
 err_cleanup_slots:
 {
        struct controller *ctrl = pci_get_drvdata(dev);
 
+       dev->shpc_managed = 0;
        shpchp_remove_ctrl_files(ctrl);
        ctrl->hpc_ops->release_ctlr(ctrl);
        kfree(ctrl);
 
  */
 bool shpchp_is_native(struct pci_dev *bridge)
 {
-       const struct pci_host_bridge *host;
-
-       if (!IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC))
-               return false;
-
-       /*
-        * It is assumed that AMD GOLAM chips support SHPC but they do not
-        * have SHPC capability.
-        */
-       if (bridge->vendor == PCI_VENDOR_ID_AMD &&
-           bridge->device == PCI_DEVICE_ID_AMD_GOLAM_7450)
-               return true;
-
-       if (!pci_find_capability(bridge, PCI_CAP_ID_SHPC))
-               return false;
-
-       host = pci_find_host_bridge(bridge->bus);
-       return host->native_shpc_hotplug;
+       return bridge->shpc_managed;
 }
 
 /**