/* ------------------------------------------------------------------------- */
-long int
-initdram (int board_type)
+long int initdram (int board_type)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- long int size_b0;
- long int size8, size9;
- int i;
-
- /*
- * Configure UPMA for SDRAM
- */
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- memctl->memc_mptpr = CFG_MPTPR;
-
- /* burst length=4, burst type=sequential, CAS latency=2 */
- memctl->memc_mar = CFG_MAR;
-
- /*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or3 = CFG_OR3_PRELIM;
- memctl->memc_br3 = CFG_BR3_PRELIM;
-
- /* initialize memory address register */
- memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */
-
- /* mode initialization (offset 5) */
- udelay(200); /* 0x80006105 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x05);
-
- /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
- udelay(1); /* 0x80006130 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
- udelay(1); /* 0x80006130 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
-
- udelay(1); /* 0x80006106 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06);
-
- memctl->memc_mamr |= MAMR_PTBE; /* refresh enabled */
-
- udelay(200);
-
- /* Need at least 10 DRAM accesses to stabilize */
- for (i=0; i<10; ++i) {
- volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE3_PRELIM;
- unsigned long val;
-
- val = *(addr + i);
- *(addr + i) = val;
- }
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration at 9 columns */
- size_b0 = size9;
- memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTBE;
- udelay(500);
- } else { /* back to 8 columns */
- size_b0 = size8;
- memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE;
- udelay(500);
- }
-
- /*
- * Final mapping:
- */
-
- memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | \
- OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
- memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
- udelay(1000);
-
- return (size_b0);
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
+ long int size_b0;
+ long int size8, size9;
+ int i;
+
+ /*
+ * Configure UPMA for SDRAM
+ */
+ upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+ memctl->memc_mptpr = CFG_MPTPR;
+
+ /* burst length=4, burst type=sequential, CAS latency=2 */
+ memctl->memc_mar = CFG_MAR;
+
+ /*
+ * Map controller bank 3 to the SDRAM bank at preliminary address.
+ */
+ memctl->memc_or3 = CFG_OR3_PRELIM;
+ memctl->memc_br3 = CFG_BR3_PRELIM;
+
+ /* initialize memory address register */
+ memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */
+
+ /* mode initialization (offset 5) */
+ udelay (200); /* 0x80006105 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
+
+ /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
+ udelay (1); /* 0x80006130 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
+ udelay (1); /* 0x80006130 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
+
+ udelay (1); /* 0x80006106 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
+
+ memctl->memc_mamr |= MAMR_PTBE; /* refresh enabled */
+
+ udelay (200);
+
+ /* Need at least 10 DRAM accesses to stabilize */
+ for (i = 0; i < 10; ++i) {
+ volatile unsigned long *addr =
+ (volatile unsigned long *) SDRAM_BASE3_PRELIM;
+ unsigned long val;
+
+ val = *(addr + i);
+ *(addr + i) = val;
+ }
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ * try 8 column mode
+ */
+ size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+ udelay (1000);
+
+ /*
+ * try 9 column mode
+ */
+ size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+ if (size8 < size9) { /* leave configuration at 9 columns */
+ size_b0 = size9;
+ memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTBE;
+ udelay (500);
+ } else { /* back to 8 columns */
+ size_b0 = size8;
+ memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE;
+ udelay (500);
+ }
+
+ /*
+ * Final mapping:
+ */
+
+ memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) |
+ OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
+ memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+ udelay (1000);
+
+ return (size_b0);
}
/* ------------------------------------------------------------------------- */
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- memctl->memc_mamr = mamr_value;
-
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
+ volatile long int *addr;
+ ulong cnt, val;
+ ulong save[32]; /* to make test non-destructive */
+ unsigned char i = 0;
+
+ memctl->memc_mamr = mamr_value;
+
+ for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ save[i++] = *addr;
+ *addr = ~cnt;
+ }
- for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
+ /* write 0 to base address */
+ addr = base;
+ save[i] = *addr;
+ *addr = 0;
- val = *addr;
- *addr = save[--i];
+ /* check at base address */
+ if ((val = *addr) != 0) {
+ *addr = save[i];
+ return (0);
+ }
+
+ for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ val = *addr;
+ *addr = save[--i];
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
+ if (val != (~cnt)) {
+ return (cnt * sizeof (long));
+ }
}
- }
- return (maxsize);
+ return (maxsize);
}
/* ------------------------------------------------------------------------- */
int board_pre_init (void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
/* Disable Ethernet TENA on Port B
* Necessary because of pull up in COM3 port.
*
- * This is just a preliminary fix, intended to turn off TENA
- * as soon as possible to avoid noise on the network. Once
- * I²C is running we will make sure the interface is
- * correctly initialized.
+ * This is just a preliminary fix, intended to turn off TENA
+ * as soon as possible to avoid noise on the network. Once
+ * I²C is running we will make sure the interface is
+ * correctly initialized.
*/
immr->im_cpm.cp_pbpar &= ~PB_ENET_TENA;
immr->im_cpm.cp_pbodr &= ~PB_ENET_TENA;
- immr->im_cpm.cp_pbdat &= ~PB_ENET_TENA; /* set to 0 = disabled */
- immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
+ immr->im_cpm.cp_pbdat &= ~PB_ENET_TENA; /* set to 0 = disabled */
+ immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
return (0);
}
/* ------------------------------------------------------------------------- */
-void reset_phy(void)
+void reset_phy (void)
{
uchar c;
#ifdef DEBUG
printf ("### Switch on Ethernet for SCC2 ###\n");
#endif
- c = pic_read (0x61);
+ c = pic_read (0x61);
#ifdef DEBUG
printf ("Old PIC read: reg_61 = 0x%02x\n", c);
#endif
- c |= 0x40; /* disable COM3 */
- c &= ~0x80; /* enable Ethernet */
+ c |= 0x40; /* disable COM3 */
+ c &= ~0x80; /* enable Ethernet */
pic_write (0x61, c);
#ifdef DEBUG
- c = pic_read (0x61);
+ c = pic_read (0x61);
printf ("New PIC read: reg_61 = 0x%02x\n", c);
#endif
- udelay(1000);
+ udelay (1000);
}
/*-----------------------------------------------------------------------
/* Number of bytes returned from Keyboard Controller */
#define KEYBD_VERSIONLEN 2 /* version information */
-#define KEYBD_DATALEN 9 /* normal key scan data */
+#define KEYBD_DATALEN 9 /* normal key scan data */
/* maximum number of "magic" key codes that can be assigned */
#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */
-void misc_init_r (bd_t *bd)
+void misc_init_r (bd_t * bd)
{
- uchar kbd_data [KEYBD_DATALEN];
- uchar keybd_env[2*KEYBD_DATALEN+1];
+ uchar kbd_data[KEYBD_DATALEN];
+ uchar keybd_env[2 * KEYBD_DATALEN + 1];
uchar val, errcd;
uchar *str;
int i;
/* Read initial keyboard error code */
val = KEYBD_CMD_READ_STATUS;
i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, &errcd, 1);
+ i2c_read (kbd_addr, 0, 0, &errcd, 1);
if (errcd) {
printf ("KEYBD: Error %02X\n", errcd);
}
i2c_write (kbd_addr, 0, 0, &val, 1);
val = KEYBD_CMD_READ_STATUS;
i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, &val, 1);
- if (val) { /* permanent error, report it */
+ if (val) { /* permanent error, report it */
printf ("*** Keyboard error code %02X ***\n", val);
sprintf (keybd_env, "%02X", val);
setenv ("keybd", keybd_env);
return;
}
- /*
- * Now we know that we have a working keyboard, so disable
- * all output to the LCD except when a key press is detected.
+ /*
+ * Now we know that we have a working keyboard, so disable
+ * all output to the LCD except when a key press is detected.
*/
if ((console_assign (stdout, "serial") < 0) ||
- (console_assign (stderr, "serial") < 0) ) {
+ (console_assign (stderr, "serial") < 0)) {
printf ("Can't assign serial port as output device\n");
}
/* Read Version */
val = KEYBD_CMD_READ_VERSION;
i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
/* Read keys */
val = KEYBD_CMD_READ_KEYS;
i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
- for (i=0; i<KEYBD_DATALEN; ++i) {
- sprintf(keybd_env+i+i, "%02X", kbd_data[i]);
+ for (i = 0; i < KEYBD_DATALEN; ++i) {
+ sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
}
setenv ("keybd", keybd_env);
- str = strdup (key_match(kbd_data)); /* decode keys */
+ str = strdup (key_match (kbd_data)); /* decode keys */
#ifdef KEYBD_SET_DEBUGMODE
- if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */
+ if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */
if ((console_assign (stdout, "lcd") < 0) ||
- (console_assign (stderr, "lcd") < 0) ) {
+ (console_assign (stderr, "lcd") < 0)) {
printf ("Can't assign LCD display as output device\n");
}
}
-#endif /* KEYBD_SET_DEBUGMODE */
-#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
- setenv ("preboot", str); /* set or delete definition */
-#endif /* CONFIG_PREBOOT */
+#endif /* KEYBD_SET_DEBUGMODE */
+#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
+ setenv ("preboot", str); /* set or delete definition */
+#endif /* CONFIG_PREBOOT */
if (str != NULL) {
free (str);
}
*/
#ifdef CONFIG_PREBOOT
-static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_magic_prefix[] = "key_magic";
static uchar kbd_command_prefix[] = "key_cmd";
-static uchar *key_match (uchar *kbd_data)
+static uchar *key_match (uchar * kbd_data)
{
uchar compare[KEYBD_DATALEN];
- uchar magic[sizeof(kbd_magic_prefix) + 1];
+ uchar magic[sizeof (kbd_magic_prefix) + 1];
uchar extra;
uchar *str, *nxt, *suffix;
uchar *kbd_magic_keys;
* "key_magic" is checked (old behaviour); the string "125" causes
* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
*/
- if ((kbd_magic_keys = getenv("magic_keys")) == NULL)
+ if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
kbd_magic_keys = "";
/* loop over all magic keys;
extra = 0;
- for (str=getenv (magic); str != NULL; str = (*nxt) ? nxt+1 : nxt) {
+ for (str= getenv(magic); str != NULL; str = (*nxt) ? nxt+1 : nxt) {
uchar c;
int k;
- c = (uchar)simple_strtoul(str, (char **)(&nxt), 16);
+ c = (uchar) simple_strtoul (str, (char **) (&nxt), 16);
if (str == nxt) { /* invalid character */
break;
* Set matches to zero, so they match only once
* and we can find duplicates or extra keys
*/
- for (k=0; k<KEYBD_DATALEN; ++k) {
+ for (k = 0; k < KEYBD_DATALEN; ++k) {
if (compare[k] == '\0') /* only non-zero entries */
continue;
if (c == compare[k]) { /* found matching key */
* and has no extra keys
*/
- for (i=0; i<KEYBD_DATALEN; ++i) {
+ for (i = 0; i < KEYBD_DATALEN; ++i) {
if (compare[i])
break;
}
if ((i == KEYBD_DATALEN) && (extra == 0)) {
- uchar cmd_name[sizeof(kbd_command_prefix) + 1];
+ uchar cmd_name[sizeof (kbd_command_prefix) + 1];
char *cmd;
sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
cmd = getenv (cmd_name);
#if 0
printf ("### Set PREBOOT to $(%s): \"%s\"\n",
- cmd_name, cmd ? cmd : "<<NULL>>");
+ cmd_name, cmd ? cmd : "<<NULL>>");
#endif
*kbd_data = *suffix;
return (cmd);
*kbd_data = '\0';
return (NULL);
}
-#endif /* CONFIG_PREBOOT */
+#endif /* CONFIG_PREBOOT */
/*-----------------------------------------------------------------------
* Board Special Commands: PIC read/write
*/
#if (CONFIG_COMMANDS & CFG_CMD_BSP)
-int do_pic (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+int do_pic (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
uchar reg, val;
switch (argc) {
- case 3: /* PIC read reg */
- if (strcmp(argv[1],"read") != 0)
+ case 3: /* PIC read reg */
+ if (strcmp (argv[1], "read") != 0)
break;
- reg = simple_strtoul(argv[2], NULL, 16);
+ reg = simple_strtoul (argv[2], NULL, 16);
printf ("PIC read: reg %02x: %02x\n\n", reg, pic_read (reg));
return 0;
- case 4: /* PIC write reg val */
- if (strcmp(argv[1],"write") != 0)
+ case 4: /* PIC write reg val */
+ if (strcmp (argv[1], "write") != 0)
break;
- reg = simple_strtoul(argv[2], NULL, 16);
- val = simple_strtoul(argv[3], NULL, 16);
+ reg = simple_strtoul (argv[2], NULL, 16);
+ val = simple_strtoul (argv[3], NULL, 16);
printf ("PIC write: reg %02x val 0x%02x: %02x => ",
- reg, val, pic_read (reg));
+ reg, val, pic_read (reg));
pic_write (reg, val);
printf ("%02x\n\n", pic_read (reg));
return 0;
}
/* Read Keyboard status */
-int do_kbd (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+int do_kbd (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
- uchar kbd_data [KEYBD_DATALEN];
- uchar keybd_env[2*KEYBD_DATALEN+1];
+ uchar kbd_data[KEYBD_DATALEN];
+ uchar keybd_env[2 * KEYBD_DATALEN + 1];
uchar val;
int i;
/* Read keys */
val = KEYBD_CMD_READ_KEYS;
i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
puts ("Keys:");
- for (i=0; i<KEYBD_DATALEN; ++i) {
- sprintf(keybd_env+i+i, "%02X", kbd_data[i]);
+ for (i = 0; i < KEYBD_DATALEN; ++i) {
+ sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
printf (" %02x", kbd_data[i]);
}
putc ('\n');
/* Read and set LSB switch */
#define CFG_PC_TXD1_ENA 0x0008
-int do_lsb (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+int do_lsb (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
uchar val;
- immap_t *immr = (immap_t *)CFG_IMMR;
+ immap_t *immr = (immap_t *) CFG_IMMR;
switch (argc) {
- case 1: /* lsb - print setting */
+ case 1: /* lsb - print setting */
val = pic_read (0x60);
printf ("LSB is o%s\n", (val & 0x20) ? "n" : "ff");
return 0;
- case 2: /* lsb on or lsb off - set switch */
+ case 2: /* lsb on or lsb off - set switch */
val = pic_read (0x60);
- if (strcmp(argv[1],"on") == 0) {
- val |= 0x20;
+ if (strcmp (argv[1], "on") == 0) {
+ val |= 0x20;
immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA);
- immr->im_ioport.iop_pcdat |= CFG_PC_TXD1_ENA;
- immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA;
- } else if (strcmp(argv[1],"off") == 0) {
+ immr->im_ioport.iop_pcdat |= CFG_PC_TXD1_ENA;
+ immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA;
+ } else if (strcmp (argv[1], "off") == 0) {
val &= ~0x20;
immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA);
immr->im_ioport.iop_pcdat &= ~(CFG_PC_TXD1_ENA);
- immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA;
+ immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA;
} else {
break;
}
return 1;
}
-#endif /* CFG_CMD_BSP */
+#endif /* CFG_CMD_BSP */
/*-----------------------------------------------------------------------
* Utilities
uchar pic_read (uchar reg)
{
- return (i2c_reg_read(CFG_I2C_PICIO_ADDR, reg));
+ return (i2c_reg_read (CFG_I2C_PICIO_ADDR, reg));
}
void pic_write (uchar reg, uchar val)
{
- i2c_reg_write(CFG_I2C_PICIO_ADDR, reg, val);
+ i2c_reg_write (CFG_I2C_PICIO_ADDR, reg, val);
}
projects / users / rw / ppcboot.git / commitdiff