.sysc = &omap2420_dss_sysc,
 };
 
-/* dss */
-static struct omap_hwmod_irq_info omap2420_dss_irqs[] = {
-       { .irq = 25 },
-};
-
 static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
        { .name = "dispc", .dma_req = 5 },
 };
        .name           = "dss_core",
        .class          = &omap2420_dss_hwmod_class,
        .main_clk       = "dss1_fck", /* instead of dss_fck */
-       .mpu_irqs       = omap2420_dss_irqs,
-       .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_dss_irqs),
        .sdma_reqs      = omap2420_dss_sdma_chs,
        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_dss_sdma_chs),
        .prcm           = {
        .sysc = &omap2420_dispc_sysc,
 };
 
+static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
+       { .irq = 25 },
+};
+
 static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
        {
                .pa_start       = 0x48050400,
 static struct omap_hwmod omap2420_dss_dispc_hwmod = {
        .name           = "dss_dispc",
        .class          = &omap2420_dispc_hwmod_class,
+       .mpu_irqs       = omap2420_dispc_irqs,
+       .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_dispc_irqs),
        .main_clk       = "dss1_fck",
        .prcm           = {
                .omap2 = {
 
        .sysc = &omap2430_dss_sysc,
 };
 
-/* dss */
-static struct omap_hwmod_irq_info omap2430_dss_irqs[] = {
-       { .irq = 25 },
-};
 static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
        { .name = "dispc", .dma_req = 5 },
 };
        .name           = "dss_core",
        .class          = &omap2430_dss_hwmod_class,
        .main_clk       = "dss1_fck", /* instead of dss_fck */
-       .mpu_irqs       = omap2430_dss_irqs,
-       .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dss_irqs),
        .sdma_reqs      = omap2430_dss_sdma_chs,
        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_dss_sdma_chs),
        .prcm           = {
        .sysc = &omap2430_dispc_sysc,
 };
 
+static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
+       { .irq = 25 },
+};
+
 static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
        {
                .pa_start       = 0x48050400,
 static struct omap_hwmod omap2430_dss_dispc_hwmod = {
        .name           = "dss_dispc",
        .class          = &omap2430_dispc_hwmod_class,
+       .mpu_irqs       = omap2430_dispc_irqs,
+       .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dispc_irqs),
        .main_clk       = "dss1_fck",
        .prcm           = {
                .omap2 = {
 
        .sysc = &omap3xxx_dss_sysc,
 };
 
-/* dss */
-static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
-       { .irq = 25 },
-};
-
 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
        { .name = "dispc", .dma_req = 5 },
        { .name = "dsi1", .dma_req = 74 },
        .name           = "dss_core",
        .class          = &omap3xxx_dss_hwmod_class,
        .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
-       .mpu_irqs       = omap3xxx_dss_irqs,
-       .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dss_irqs),
        .sdma_reqs      = omap3xxx_dss_sdma_chs,
        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
 
        .name           = "dss_core",
        .class          = &omap3xxx_dss_hwmod_class,
        .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
-       .mpu_irqs       = omap3xxx_dss_irqs,
-       .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dss_irqs),
        .sdma_reqs      = omap3xxx_dss_sdma_chs,
        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
 
        .sysc = &omap3xxx_dispc_sysc,
 };
 
+static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
+       { .irq = 25 },
+};
+
 static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
        {
                .pa_start       = 0x48050400,
 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
        .name           = "dss_dispc",
        .class          = &omap3xxx_dispc_hwmod_class,
+       .mpu_irqs       = omap3xxx_dispc_irqs,
+       .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dispc_irqs),
        .main_clk       = "dss1_alwon_fck",
        .prcm           = {
                .omap2 = {
        .name = "dsi",
 };
 
+static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
+       { .irq = 25 },
+};
+
 /* dss_dsi1 */
 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
        {
 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
        .name           = "dss_dsi1",
        .class          = &omap3xxx_dsi_hwmod_class,
+       .mpu_irqs       = omap3xxx_dsi1_irqs,
+       .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dsi1_irqs),
        .main_clk       = "dss1_alwon_fck",
        .prcm           = {
                .omap2 = {
 
 #include <linux/delay.h>
 #include <linux/workqueue.h>
 #include <linux/hardirq.h>
+#include <linux/interrupt.h>
 
 #include <plat/sram.h>
 #include <plat/clock.h>
 static struct {
        struct platform_device *pdev;
        void __iomem    *base;
+       int irq;
 
        u32     fifo_size[3];
 
  * but we presume they are on because we got an IRQ. However,
  * an irq handler may turn the clocks off, so we may not have
  * clock later in the function. */
-void dispc_irq_handler(void)
+static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
 {
        int i;
-       u32 irqstatus;
+       u32 irqstatus, irqenable;
        u32 handledirqs = 0;
        u32 unhandled_errors;
        struct omap_dispc_isr_data *isr_data;
        spin_lock(&dispc.irq_lock);
 
        irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
+       irqenable = dispc_read_reg(DISPC_IRQENABLE);
+
+       /* IRQ is not for us */
+       if (!(irqstatus & irqenable)) {
+               spin_unlock(&dispc.irq_lock);
+               return IRQ_NONE;
+       }
 
 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
        spin_lock(&dispc.irq_stats_lock);
        }
 
        spin_unlock(&dispc.irq_lock);
+
+       return IRQ_HANDLED;
 }
 
 static void dispc_error_worker(struct work_struct *work)
 static int omap_dispchw_probe(struct platform_device *pdev)
 {
        u32 rev;
+       int r = 0;
        struct resource *dispc_mem;
 
        dispc.pdev = pdev;
        dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
        if (!dispc_mem) {
                DSSERR("can't get IORESOURCE_MEM DISPC\n");
-               return -EINVAL;
+               r = -EINVAL;
+               goto fail0;
        }
        dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
        if (!dispc.base) {
                DSSERR("can't ioremap DISPC\n");
-               return -ENOMEM;
+               r = -ENOMEM;
+               goto fail0;
+       }
+       dispc.irq = platform_get_irq(dispc.pdev, 0);
+       if (dispc.irq < 0) {
+               DSSERR("platform_get_irq failed\n");
+               r = -ENODEV;
+               goto fail1;
+       }
+
+       r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
+               "OMAP DISPC", dispc.pdev);
+       if (r < 0) {
+               DSSERR("request_irq failed\n");
+               goto fail1;
        }
 
        enable_clocks(1);
        enable_clocks(0);
 
        return 0;
+fail1:
+       iounmap(dispc.base);
+fail0:
+       return r;
 }
 
 static int omap_dispchw_remove(struct platform_device *pdev)
 {
+       free_irq(dispc.irq, dispc.pdev);
        iounmap(dispc.base);
        return 0;
 }
 
 {
        struct platform_device *pdev;
        void __iomem    *base;
+       int irq;
 
        struct dsi_clock_info current_cinfo;
 
 static int debug_irq;
 
 /* called from dss */
-void dsi_irq_handler(void)
+static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
 {
        u32 irqstatus, vcstatus, ciostatus;
        int i;
 
        irqstatus = dsi_read_reg(DSI_IRQSTATUS);
 
+       /* IRQ is not for us */
+       if (!irqstatus)
+               return IRQ_NONE;
+
 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
        spin_lock(&dsi.irq_stats_lock);
        dsi.irq_stats.irq_count++;
 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
        spin_unlock(&dsi.irq_stats_lock);
 #endif
+       return IRQ_HANDLED;
 }
 
-
 static void _dsi_initialize_irq(void)
 {
        u32 l;
                r = -ENOMEM;
                goto err1;
        }
+       dsi.irq = platform_get_irq(dsi.pdev, 0);
+       if (dsi.irq < 0) {
+               DSSERR("platform_get_irq failed\n");
+               r = -ENODEV;
+               goto err2;
+       }
+
+       r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED,
+               "OMAP DSI1", dsi.pdev);
+       if (r < 0) {
+               DSSERR("request_irq failed\n");
+               goto err2;
+       }
 
        enable_clocks(1);
 
        enable_clocks(0);
 
        return 0;
+err2:
+       iounmap(dsi.base);
 err1:
        destroy_workqueue(dsi.workqueue);
        return r;
                dsi.vdds_dsi_reg = NULL;
        }
 
+       free_irq(dsi.irq, dsi.pdev);
        iounmap(dsi.base);
 
        destroy_workqueue(dsi.workqueue);
 
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/delay.h>
-#include <linux/interrupt.h>
 #include <linux/seq_file.h>
 #include <linux/clk.h>
 
        enum dss_clk_source dispc_clk_source;
 
        u32             ctx[DSS_SZ_REGS / sizeof(u32)];
-       int             dss_irq;
 } dss;
 
 static void dss_clk_enable_all_no_ctx(void);
        return 0;
 }
 
-
-
-static irqreturn_t dss_irq_handler_omap2(int irq, void *arg)
-{
-       dispc_irq_handler();
-
-       return IRQ_HANDLED;
-}
-
-static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
-{
-       u32 irqstatus;
-
-       irqstatus = dss_read_reg(DSS_IRQSTATUS);
-
-       if (irqstatus & (1<<0)) /* DISPC_IRQ */
-               dispc_irq_handler();
-#ifdef CONFIG_OMAP2_DSS_DSI
-       if (irqstatus & (1<<1)) /* DSI_IRQ */
-               dsi_irq_handler();
-#endif
-
-       return IRQ_HANDLED;
-}
-
 static int _omap_dss_wait_reset(void)
 {
        int t = 0;
        REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
 #endif
 
-       dss.dss_irq = platform_get_irq(dss.pdev, 0);
-       if (dss.dss_irq < 0) {
-               DSSERR("omap2 dss: platform_get_irq failed\n");
-               r = -ENODEV;
-               goto fail1;
-       }
-
-       r = request_irq(dss.dss_irq,
-               cpu_is_omap24xx()
-               ? dss_irq_handler_omap2
-               : dss_irq_handler_omap3,
-               0, "OMAP DSS", NULL);
-
-       if (r < 0) {
-               DSSERR("omap2 dss: request_irq failed\n");
-               goto fail1;
-       }
-
        if (cpu_is_omap34xx()) {
                dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
                if (IS_ERR(dss.dpll4_m4_ck)) {
                        DSSERR("Failed to get dpll4_m4_ck\n");
                        r = PTR_ERR(dss.dpll4_m4_ck);
-                       goto fail2;
+                       goto fail1;
                }
        }
 
 
        return 0;
 
-fail2:
-       free_irq(dss.dss_irq, NULL);
 fail1:
        iounmap(dss.base);
 fail0:
        if (cpu_is_omap34xx())
                clk_put(dss.dpll4_m4_ck);
 
-       free_irq(dss.dss_irq, NULL);
-
        iounmap(dss.base);
 }