MIPS: Clean up RDHWR handling

No preprocessor definitions are used in the handling of the registers
accessible with the RDHWR instruction, nor the corresponding bits in the
CP0 HWREna register.

Add definitions for both the register numbers (MIPS_HWR_*) and HWREna
bits (MIPS_HWRENA_*) in asm/mipsregs.h and make use of them in the
initialisation of HWREna and emulation of the RDHWR instruction.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <david.daney@cavium.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index d68e685cde6032729a5632171e163f102f6a4f42..bd8b9bbe17719df3fce2c8c9484fd9dad5eca4d4 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -55,7 +55,7 @@
 #define cpu_has_mipsmt         0
 #define cpu_has_vint           0
 #define cpu_has_veic           0
-#define cpu_hwrena_impl_bits   0xc0000000
+#define cpu_hwrena_impl_bits   (MIPS_HWRENA_IMPL1 | MIPS_HWRENA_IMPL2)
 #define cpu_has_wsbh            1
 
 #define cpu_has_rixi           (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index e1ca65c62f6a5427663fa77e567aa1d8de585b82..8b1b37d50d158fb448537059faffce2067dd32ec 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -53,7 +53,7 @@
 #define CP0_SEGCTL2 $5, 4
 #define CP0_WIRED $6
 #define CP0_INFO $7
-#define CP0_HWRENA $7, 0
+#define CP0_HWRENA $7
 #define CP0_BADVADDR $8
 #define CP0_BADINSTR $8, 1
 #define CP0_COUNT $9
@@ -853,6 +853,24 @@
 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 #define MIPS_CDMMBASE_ADDR_START 15
 
+/* RDHWR register numbers */
+#define MIPS_HWR_CPUNUM                0       /* CPU number */
+#define MIPS_HWR_SYNCISTEP     1       /* SYNCI step size */
+#define MIPS_HWR_CC            2       /* Cycle counter */
+#define MIPS_HWR_CCRES         3       /* Cycle counter resolution */
+#define MIPS_HWR_ULR           29      /* UserLocal */
+#define MIPS_HWR_IMPL1         30      /* Implementation dependent */
+#define MIPS_HWR_IMPL2         31      /* Implementation dependent */
+
+/* Bits in HWREna register */
+#define MIPS_HWRENA_CPUNUM     (_ULCAST_(1) << MIPS_HWR_CPUNUM)
+#define MIPS_HWRENA_SYNCISTEP  (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
+#define MIPS_HWRENA_CC         (_ULCAST_(1) << MIPS_HWR_CC)
+#define MIPS_HWRENA_CCRES      (_ULCAST_(1) << MIPS_HWR_CCRES)
+#define MIPS_HWRENA_ULR                (_ULCAST_(1) << MIPS_HWR_ULR)
+#define MIPS_HWRENA_IMPL1      (_ULCAST_(1) << MIPS_HWR_IMPL1)
+#define MIPS_HWRENA_IMPL2      (_ULCAST_(1) << MIPS_HWR_IMPL2)
+
 /*
  * Bitfields in the TX39 family CP0 Configuration Register 3
  */

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 66e5820bfdae4334a0a5ff5655acb3cece637f8d..7176a6057e26d63bdb41cd8762082588ffb5cd60 100644 (file)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -619,17 +619,17 @@ static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
                        1, regs, 0);
        switch (rd) {
-       case 0:         /* CPU number */
+       case MIPS_HWR_CPUNUM:           /* CPU number */
                regs->regs[rt] = smp_processor_id();
                return 0;
-       case 1:         /* SYNCI length */
+       case MIPS_HWR_SYNCISTEP:        /* SYNCI length */
                regs->regs[rt] = min(current_cpu_data.dcache.linesz,
                                     current_cpu_data.icache.linesz);
                return 0;
-       case 2:         /* Read count register */
+       case MIPS_HWR_CC:               /* Read count register */
                regs->regs[rt] = read_c0_count();
                return 0;
-       case 3:         /* Count register resolution */
+       case MIPS_HWR_CCRES:            /* Count register resolution */
                switch (current_cpu_type()) {
                case CPU_20KC:
                case CPU_25KF:
@@ -639,7 +639,7 @@ static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
                        regs->regs[rt] = 2;
                }
                return 0;
-       case 29:
+       case MIPS_HWR_ULR:              /* Read UserLocal register */
                regs->regs[rt] = ti->tp_value;
                return 0;
        default:
@@ -2070,10 +2070,13 @@ static void configure_hwrena(void)
        unsigned int hwrena = cpu_hwrena_impl_bits;
 
        if (cpu_has_mips_r2_r6)
-               hwrena |= 0x0000000f;
+               hwrena |= MIPS_HWRENA_CPUNUM |
+                         MIPS_HWRENA_SYNCISTEP |
+                         MIPS_HWRENA_CC |
+                         MIPS_HWRENA_CCRES;
 
        if (!noulri && cpu_has_userlocal)
-               hwrena |= (1 << 29);
+               hwrena |= MIPS_HWRENA_ULR;
 
        if (hwrena)
                write_c0_hwrena(hwrena);

diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c
index 80bb6212a06735f68c20a71ad9568328a5f2bd85..892f36f56d32e60975ba2b0d97af6f7a50e1f4c6 100644 (file)
--- a/arch/mips/kvm/emulate.c
+++ b/arch/mips/kvm/emulate.c
@@ -2296,17 +2296,17 @@ enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc,
                        goto emulate_ri;
                }
                switch (rd) {
-               case 0: /* CPU number */
+               case MIPS_HWR_CPUNUM:           /* CPU number */
                        arch->gprs[rt] = 0;
                        break;
-               case 1: /* SYNCI length */
+               case MIPS_HWR_SYNCISTEP:        /* SYNCI length */
                        arch->gprs[rt] = min(current_cpu_data.dcache.linesz,
                                             current_cpu_data.icache.linesz);
                        break;
-               case 2: /* Read count register */
+               case MIPS_HWR_CC:               /* Read count register */
                        arch->gprs[rt] = kvm_mips_read_count(vcpu);
                        break;
-               case 3: /* Count register resolution */
+               case MIPS_HWR_CCRES:            /* Count register resolution */
                        switch (current_cpu_data.cputype) {
                        case CPU_20KC:
                        case CPU_25KF:
@@ -2316,7 +2316,7 @@ enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc,
                                arch->gprs[rt] = 2;
                        }
                        break;
-               case 29:
+               case MIPS_HWR_ULR:              /* Read UserLocal register */
                        arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0);
                        break;