]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
tg3: Fix RSS indirection table distribution
authorMatt Carlson <mcarlson@broadcom.com>
Wed, 20 Jul 2011 10:20:54 +0000 (10:20 +0000)
committerJoe Jin <joe.jin@oracle.com>
Tue, 15 May 2012 08:37:04 +0000 (16:37 +0800)
The current RSS indirection table is populated such that more traffic
will hit the first RSS ring.  This patch adjusts the indirection table
so that the load is more evenly distributed.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 9d53fa129628d4899083b06fa66b7ca10fed8eb4)

Signed-off-by: Joe Jin <joe.jin@oracle.com>
drivers/net/tg3.c

index 64d8711b53e31350ddf535a0ffc11728458a940f..10d5c5ef322408bb7a4c3d6ad39904232fbf517d 100644 (file)
@@ -8721,15 +8721,24 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        udelay(100);
 
        if (tg3_flag(tp, ENABLE_RSS)) {
+               int i = 0;
                u32 reg = MAC_RSS_INDIR_TBL_0;
-               u8 *ent = (u8 *)&val;
 
-               /* Setup the indirection table */
-               for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
-                       int idx = i % sizeof(val);
+               if (tp->irq_cnt == 2) {
+                       for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i += 8) {
+                               tw32(reg, 0x0);
+                               reg += 4;
+                       }
+               } else {
+                       u32 val;
 
-                       ent[idx] = i % (tp->irq_cnt - 1);
-                       if (idx == sizeof(val) - 1) {
+                       while (i < TG3_RSS_INDIR_TBL_SIZE) {
+                               val = i % (tp->irq_cnt - 1);
+                               i++;
+                               for (; i % 8; i++) {
+                                       val <<= 4;
+                                       val |= (i % (tp->irq_cnt - 1));
+                               }
                                tw32(reg, val);
                                reg += 4;
                        }