x86/fpu: Remove fpstate_sanitize_xstate()

No more users.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20210623121453.124819167@linutronix.de

diff --git a/arch/x86/include/asm/fpu/internal.h b/arch/x86/include/asm/fpu/internal.h
index 9ed98460959516f3b186e121957850c9a59a7139..0148791acc49264d44793afa529e2db43e69ec37 100644 (file)
--- a/arch/x86/include/asm/fpu/internal.h
+++ b/arch/x86/include/asm/fpu/internal.h
@@ -86,8 +86,6 @@ extern void fpstate_init_soft(struct swregs_state *soft);
 static inline void fpstate_init_soft(struct swregs_state *soft) {}
 #endif
 
-extern void fpstate_sanitize_xstate(struct fpu *fpu);
-
 #define user_insn(insn, output, input...)                              \
 ({                                                                     \
        int err;                                                        \

diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index 8d023a26ae222eed1166683916dd43ac0e2b166b..e17fde9b1ca3d8a42db07d0d5ff88fc660e5f65f 100644 (file)
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -128,85 +128,6 @@ static bool xfeature_is_supervisor(int xfeature_nr)
        return ecx & 1;
 }
 
-/*
- * When executing XSAVEOPT (or other optimized XSAVE instructions), if
- * a processor implementation detects that an FPU state component is still
- * (or is again) in its initialized state, it may clear the corresponding
- * bit in the header.xfeatures field, and can skip the writeout of registers
- * to the corresponding memory layout.
- *
- * This means that when the bit is zero, the state component might still contain
- * some previous - non-initialized register state.
- *
- * Before writing xstate information to user-space we sanitize those components,
- * to always ensure that the memory layout of a feature will be in the init state
- * if the corresponding header bit is zero. This is to ensure that user-space doesn't
- * see some stale state in the memory layout during signal handling, debugging etc.
- */
-void fpstate_sanitize_xstate(struct fpu *fpu)
-{
-       struct fxregs_state *fx = &fpu->state.fxsave;
-       int feature_bit;
-       u64 xfeatures;
-
-       if (!use_xsaveopt())
-               return;
-
-       xfeatures = fpu->state.xsave.header.xfeatures;
-
-       /*
-        * None of the feature bits are in init state. So nothing else
-        * to do for us, as the memory layout is up to date.
-        */
-       if ((xfeatures & xfeatures_mask_all) == xfeatures_mask_all)
-               return;
-
-       /*
-        * FP is in init state
-        */
-       if (!(xfeatures & XFEATURE_MASK_FP)) {
-               fx->cwd = 0x37f;
-               fx->swd = 0;
-               fx->twd = 0;
-               fx->fop = 0;
-               fx->rip = 0;
-               fx->rdp = 0;
-               memset(fx->st_space, 0, sizeof(fx->st_space));
-       }
-
-       /*
-        * SSE is in init state
-        */
-       if (!(xfeatures & XFEATURE_MASK_SSE))
-               memset(fx->xmm_space, 0, sizeof(fx->xmm_space));
-
-       /*
-        * First two features are FPU and SSE, which above we handled
-        * in a special way already:
-        */
-       feature_bit = 0x2;
-       xfeatures = (xfeatures_mask_user() & ~xfeatures) >> 2;
-
-       /*
-        * Update all the remaining memory layouts according to their
-        * standard xstate layout, if their header bit is in the init
-        * state:
-        */
-       while (xfeatures) {
-               if (xfeatures & 0x1) {
-                       int offset = xstate_comp_offsets[feature_bit];
-                       int size = xstate_sizes[feature_bit];
-
-                       memcpy((void *)fx + offset,
-                              (void *)&init_fpstate.xsave + offset,
-                              size);
-               }
-
-               xfeatures >>= 1;
-               feature_bit++;
-       }
-}
-
 /*
  * Enable the extended processor state save/restore feature.
  * Called once per CPU onlining.