struct hnae3_handle *nic = &vport->nic;
        struct hnae3_knic_private_info *kinfo = &nic->kinfo;
        struct hclge_dev *hdev = vport->back;
-       int i, ret;
+       int ret;
 
        kinfo->num_desc = num_desc;
        kinfo->rx_buf_len = hdev->rx_buf_len;
                = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
        kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
 
-       for (i = 0; i < HNAE3_MAX_TC; i++) {
-               if (hdev->hw_tc_map & BIT(i)) {
-                       kinfo->tc_info[i].enable = true;
-                       kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
-                       kinfo->tc_info[i].tqp_count = kinfo->rss_size;
-                       kinfo->tc_info[i].tc = i;
-               } else {
-                       /* Set to default queue if TC is disable */
-                       kinfo->tc_info[i].enable = false;
-                       kinfo->tc_info[i].tqp_offset = 0;
-                       kinfo->tc_info[i].tqp_count = 1;
-                       kinfo->tc_info[i].tc = 0;
-               }
-       }
-
        kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
                                  sizeof(struct hnae3_queue *), GFP_KERNEL);
        if (!kinfo->tqp)
 
        vport->dwrr = 100;  /* 100 percent as init */
        vport->alloc_rss_size = kinfo->rss_size;
 
-       for (i = 0; i < kinfo->num_tc; i++) {
+       for (i = 0; i < HNAE3_MAX_TC; i++) {
                if (hdev->hw_tc_map & BIT(i)) {
                        kinfo->tc_info[i].enable = true;
                        kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;