static int smu_disable_dpms(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
-       uint64_t features_to_disable;
        int ret = 0;
        bool use_baco = !smu->is_apu &&
                ((adev->in_gpu_reset &&
         * BACO feature has to be kept enabled.
         */
        if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
-               features_to_disable = U64_MAX &
-                       ~(1ULL << smu_cmn_to_asic_specific_index(smu,
-                                                       CMN2ASIC_MAPPING_FEATURE,
-                                                       SMU_FEATURE_BACO_BIT));
-               ret = smu_feature_update_enable_state(smu,
-                                                     features_to_disable,
-                                                     0);
+               ret = smu_disable_all_features_with_exception(smu,
+                                                             SMU_FEATURE_BACO_BIT);
                if (ret)
                        dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
        } else {
 
        .set_allowed_mask = smu_v11_0_set_allowed_mask,
        .get_enabled_mask = smu_cmn_get_enabled_mask,
        .feature_is_enabled = smu_cmn_feature_is_enabled,
+       .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
        .notify_display_change = NULL,
        .set_power_limit = smu_v11_0_set_power_limit,
        .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
 
        int (*set_allowed_mask)(struct smu_context *smu);
        int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
        int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);
+       int (*disable_all_features_with_exception)(struct smu_context *smu, enum smu_feature_mask mask);
        int (*notify_display_change)(struct smu_context *smu);
        int (*set_power_limit)(struct smu_context *smu, uint32_t n);
        int (*init_max_sustainable_clocks)(struct smu_context *smu);
 
        .set_allowed_mask = smu_v11_0_set_allowed_mask,
        .get_enabled_mask = smu_cmn_get_enabled_mask,
        .feature_is_enabled = smu_cmn_feature_is_enabled,
+       .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
        .notify_display_change = smu_v11_0_notify_display_change,
        .set_power_limit = smu_v11_0_set_power_limit,
        .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
 
        .set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
        .get_enabled_mask = smu_cmn_get_enabled_mask,
        .feature_is_enabled = smu_cmn_feature_is_enabled,
+       .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
        .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
        .mode2_reset = smu_v12_0_mode2_reset,
        .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
 
        .set_allowed_mask = smu_v11_0_set_allowed_mask,
        .get_enabled_mask = smu_cmn_get_enabled_mask,
        .feature_is_enabled = smu_cmn_feature_is_enabled,
+       .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
        .notify_display_change = NULL,
        .set_power_limit = smu_v11_0_set_power_limit,
        .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
 
 
        return ret;
 }
+
+int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
+                                               enum smu_feature_mask mask)
+{
+       uint64_t features_to_disable = U64_MAX;
+       int skipped_feature_id;
+
+       skipped_feature_id = smu_cmn_to_asic_specific_index(smu,
+                                                           CMN2ASIC_MAPPING_FEATURE,
+                                                           mask);
+       if (skipped_feature_id < 0)
+               return -EINVAL;
+
+       features_to_disable &= ~(1ULL << skipped_feature_id);
+
+       return smu_cmn_feature_update_enable_state(smu,
+                                                  features_to_disable,
+                                                  0);
+}
 
 int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
                                uint64_t new_mask);
 
+int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
+                                               enum smu_feature_mask mask);
+
 #endif
 
 #define smu_feature_set_allowed_mask(smu)                              smu_ppt_funcs(set_allowed_mask, 0, smu)
 #define smu_feature_get_enabled_mask(smu, mask, num)                   smu_ppt_funcs(get_enabled_mask, 0, smu, mask, num)
 #define smu_feature_is_enabled(smu, mask)                              smu_ppt_funcs(feature_is_enabled, 0, smu, mask)
+#define smu_disable_all_features_with_exception(smu, mask)             smu_ppt_funcs(disable_all_features_with_exception, 0, smu, mask)
 #define smu_is_dpm_running(smu)                                                smu_ppt_funcs(is_dpm_running, 0 , smu)
 #define smu_notify_display_change(smu)                                 smu_ppt_funcs(notify_display_change, 0, smu)
 #define smu_set_default_dpm_table(smu)                                 smu_ppt_funcs(set_default_dpm_table, 0, smu)