};
 
        memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
-       calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
+       calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_RT_CFG_ALL;
        calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
 
        return iwl_trans_send_cmd(trans(priv), &cmd);
 
                                        IWL_CALIB_CFG_RX_IQ_IDX |       \
                                        IWL_CALIB_CFG_CRYSTAL_IDX)
 
+#define IWL_CALIB_RT_CFG_ALL   cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX |   \
+                                       IWL_CALIB_CFG_DC_IDX |          \
+                                       IWL_CALIB_CFG_LO_IDX |          \
+                                       IWL_CALIB_CFG_TX_IQ_IDX |       \
+                                       IWL_CALIB_CFG_RX_IQ_IDX |       \
+                                       IWL_CALIB_CFG_TEMPERATURE_IDX | \
+                                       IWL_CALIB_CFG_PAPD_IDX |        \
+                                       IWL_CALIB_CFG_TX_PWR_IDX |      \
+                                       IWL_CALIB_CFG_CRYSTAL_IDX)
+
 #define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK      cpu_to_le32(BIT(0))
 
 struct iwl_calib_cfg_elmnt_s {