}
        return;
 }
-
-static int apci1564_reset(struct comedi_device *dev)
-{
-       struct addi_private *devpriv = dev->private;
-
-       ui_Type = 0;
-
-       /* Disable the input interrupts and reset status register */
-       outl(0x0, devpriv->i_IobaseAmcc + APCI1564_DI_IRQ_REG);
-       inl(devpriv->i_IobaseAmcc + APCI1564_DI_INT_STATUS_REG);
-       outl(0x0, devpriv->i_IobaseAmcc + APCI1564_DI_INT_MODE1_REG);
-       outl(0x0, devpriv->i_IobaseAmcc + APCI1564_DI_INT_MODE2_REG);
-
-       /* Reset the output channels and disable interrupts */
-       outl(0x0, devpriv->i_IobaseAmcc + APCI1564_DO_REG);
-       outl(0x0, devpriv->i_IobaseAmcc + APCI1564_DO_INT_CTRL_REG);
-
-       /* Reset the watchdog registers */
-       addi_watchdog_reset(devpriv->i_IobaseAmcc + APCI1564_WDOG_REG);
-
-       /* Reset the timer registers */
-       outl(0x0, devpriv->i_IobaseAmcc + APCI1564_TIMER_CTRL_REG);
-       outl(0x0, devpriv->i_IobaseAmcc + APCI1564_TIMER_RELOAD_REG);
-
-       /* Reset the counter registers */
-       outl(0x0, dev->iobase + APCI1564_TCW_CTRL_REG(APCI1564_COUNTER1));
-       outl(0x0, dev->iobase + APCI1564_TCW_CTRL_REG(APCI1564_COUNTER2));
-       outl(0x0, dev->iobase + APCI1564_TCW_CTRL_REG(APCI1564_COUNTER3));
-       outl(0x0, dev->iobase + APCI1564_TCW_CTRL_REG(APCI1564_COUNTER4));
-
-       return 0;
-}
 
                .i_DoMaxdata            = 0xffffffff,
                .i_Timer                = 1,
                .interrupt              = apci1564_interrupt,
-               .reset                  = apci1564_reset,
                .timer_config           = apci1564_timer_config,
                .timer_write            = apci1564_timer_write,
                .timer_read             = apci1564_timer_read,
        return IRQ_RETVAL(1);
 }
 
-static int i_ADDI_Reset(struct comedi_device *dev)
+static int apci1564_reset(struct comedi_device *dev)
 {
-       const struct addi_board *this_board = comedi_board(dev);
+       struct addi_private *devpriv = dev->private;
+
+       ui_Type = 0;
+
+       /* Disable the input interrupts and reset status register */
+       outl(0x0, devpriv->i_IobaseAmcc + APCI1564_DI_IRQ_REG);
+       inl(devpriv->i_IobaseAmcc + APCI1564_DI_INT_STATUS_REG);
+       outl(0x0, devpriv->i_IobaseAmcc + APCI1564_DI_INT_MODE1_REG);
+       outl(0x0, devpriv->i_IobaseAmcc + APCI1564_DI_INT_MODE2_REG);
+
+       /* Reset the output channels and disable interrupts */
+       outl(0x0, devpriv->i_IobaseAmcc + APCI1564_DO_REG);
+       outl(0x0, devpriv->i_IobaseAmcc + APCI1564_DO_INT_CTRL_REG);
+
+       /* Reset the watchdog registers */
+       addi_watchdog_reset(devpriv->i_IobaseAmcc + APCI1564_WDOG_REG);
+
+       /* Reset the timer registers */
+       outl(0x0, devpriv->i_IobaseAmcc + APCI1564_TIMER_CTRL_REG);
+       outl(0x0, devpriv->i_IobaseAmcc + APCI1564_TIMER_RELOAD_REG);
+
+       /* Reset the counter registers */
+       outl(0x0, dev->iobase + APCI1564_TCW_CTRL_REG(APCI1564_COUNTER1));
+       outl(0x0, dev->iobase + APCI1564_TCW_CTRL_REG(APCI1564_COUNTER2));
+       outl(0x0, dev->iobase + APCI1564_TCW_CTRL_REG(APCI1564_COUNTER3));
+       outl(0x0, dev->iobase + APCI1564_TCW_CTRL_REG(APCI1564_COUNTER4));
 
-       this_board->reset(dev);
        return 0;
 }
 
        dev->iobase = pci_resource_start(pcidev, 1);
        devpriv->i_IobaseAmcc = pci_resource_start(pcidev, 0);
 
+       apci1564_reset(dev);
+
        if (pcidev->irq > 0) {
                ret = request_irq(pcidev->irq, v_ADDI_Interrupt, IRQF_SHARED,
                                  dev->board_name, dev);
                s->type = COMEDI_SUBD_UNUSED;
        }
 
-       i_ADDI_Reset(dev);
        return 0;
 }
 
 
        if (devpriv) {
                if (dev->iobase)
-                       i_ADDI_Reset(dev);
+                       apci1564_reset(dev);
                if (dev->irq)
                        free_irq(dev->irq, dev);
        }