KVM: arm64: Use computed FGT masks to setup FGT registers

Flip the hyervisor FGT configuration over to the computed FGT
masks.

Reviewed-by: Joey Gouly <joey.gouly@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
index 925a3288bd5be79525b6275754c398fd4c6c4c71..e8645375499dfda1f50521692f5e6937fe04a3c5 100644 (file)
--- a/arch/arm64/kvm/hyp/include/hyp/switch.h
+++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
@@ -65,12 +65,41 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
        }
 }
 
+#define reg_to_fgt_masks(reg)                                          \
+       ({                                                              \
+               struct fgt_masks *m;                                    \
+               switch(reg) {                                           \
+               case HFGRTR_EL2:                                        \
+                       m = &hfgrtr_masks;                              \
+                       break;                                          \
+               case HFGWTR_EL2:                                        \
+                       m = &hfgwtr_masks;                              \
+                       break;                                          \
+               case HFGITR_EL2:                                        \
+                       m = &hfgitr_masks;                              \
+                       break;                                          \
+               case HDFGRTR_EL2:                                       \
+                       m = &hdfgrtr_masks;                             \
+                       break;                                          \
+               case HDFGWTR_EL2:                                       \
+                       m = &hdfgwtr_masks;                             \
+                       break;                                          \
+               case HAFGRTR_EL2:                                       \
+                       m = &hafgrtr_masks;                             \
+                       break;                                          \
+               default:                                                \
+                       BUILD_BUG_ON(1);                                \
+               }                                                       \
+                                                                       \
+               m;                                                      \
+       })
+
 #define compute_clr_set(vcpu, reg, clr, set)                           \
        do {                                                            \
-               u64 hfg;                                                \
-               hfg = __vcpu_sys_reg(vcpu, reg) & ~__ ## reg ## _RES0;  \
-               set |= hfg & __ ## reg ## _MASK;                        \
-               clr |= ~hfg & __ ## reg ## _nMASK;                      \
+               u64 hfg = __vcpu_sys_reg(vcpu, reg);                    \
+               struct fgt_masks *m = reg_to_fgt_masks(reg);            \
+               set |= hfg & m->mask;                                   \
+               clr |= ~hfg & m->nmask;                                 \
        } while(0)
 
 #define reg_to_fgt_group_id(reg)                                       \
@@ -101,12 +130,14 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
 #define compute_undef_clr_set(vcpu, kvm, reg, clr, set)                        \
        do {                                                            \
                u64 hfg = kvm->arch.fgu[reg_to_fgt_group_id(reg)];      \
-               set |= hfg & __ ## reg ## _MASK;                        \
-               clr |= hfg & __ ## reg ## _nMASK;                       \
+               struct fgt_masks *m = reg_to_fgt_masks(reg);            \
+               set |= hfg & m->mask;                                   \
+               clr |= hfg & m->nmask;                                  \
        } while(0)
 
 #define update_fgt_traps_cs(hctxt, vcpu, kvm, reg, clr, set)           \
        do {                                                            \
+               struct fgt_masks *m = reg_to_fgt_masks(reg);            \
                u64 c = clr, s = set;                                   \
                u64 val;                                                \
                                                                        \
@@ -116,7 +147,7 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
                                                                        \
                compute_undef_clr_set(vcpu, kvm, reg, c, s);            \
                                                                        \
-               val = __ ## reg ## _nMASK;                              \
+               val = m->nmask;                                         \
                val |= s;                                               \
                val &= ~c;                                              \
                write_sysreg_s(val, SYS_ ## reg);                       \